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參數(shù)資料
| 型號： | W78E858A40PL |
| 廠商： | Nuvoton Technology Corporation of America |
| 文件頁數(shù)： | 32/35頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 8-BIT 32K FLASH 44-PLCC |
| 標準包裝： | 30 |
| 系列： | W78 |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | EBI/EMI，串行端口 |
| 外圍設備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 36 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 768 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 44-PLCC |
| 包裝： | 管件 |
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W78E858
Publication Release Date: April 22, 2008
- 6 -
Revision A8
5. FUNCTIONAL DESCRIPTION
The W78E858 architecture consists of a core controller surrounded by various registers, four 8-bit
general purpose I/O ports, one 4-bits general purpose I/O port, 256 bytes data RAM and 512 bytes
auxiliary RAM, 128 bytes embedded EEPROM memory, three timer/counters, one serial port, 17-bit
watch-dog timer, 8-bit four channels PWM, programmable timer2 clock output, extra external interrupts
INT2 to INT9, power-down wake up via external interrupts INT0
INT9. The CPU supports 111
different op-codes and references both a 64K program address space and a 64 K data storage space.
5.1 RAM
The internal data RAM in W78E858 is 768 bytes. It is divided into two banks: 256 bytes of data RAM
and 512 bytes of auxiliary RAM. These RAM are addressed by different ways.
RAM 00H 7FH can be addressed directly and indirectly as the same as in 80C51. Address
pointers are R0 and R1 of the selected register bank.
RAM 80H FFH can only be addressed indirectly as the same as in 80C51. Address pointers are
R0, R1 of the selected registers bank.
Auxiliary RAM 0000H 01FFH is addressed indirectly as the same way to access external data
memory with the MOVX instruction. Address pointers are R0 and R1 of the selected register bank
and DPTR register. By setting ENAUXRAM flag in CHPCON register bit4 to enable on-chip
auxiliary RAM 512 bytes. When the auxiliary RAM is enabled, the data and address will not appear
on P0 and P2, they will keep their previous status that before the MOVX instruction be executed.
Write the page select 00H or 01H to MXPSR register if R0 and R1 are used as address pointer.
When the address of external data memory locations higher than 01FFH or disable auxiliary RAM
512 bytes micro-controller will be performed with the MOVX instruction in the same way as in the
80C51. The auxiliary RAM 512 bytes default is disabled after chip reset.
5.2 EEPROM
The 128 bytes EEPROM is defined in external data memory space that located in FF80H-FFFFH in
standard 8-bit series. It is accessed the same as auxiliary RAM512 bytes, the ENEEPROM flag in
CHPCON register bit5 is set. Write the page select 02H to MXPSR register, R0 and R1are used as
address pointer. The EEPROM provided byte write, page write mode and software write protection is
used to protect the data lose when power on or noise. They are described as below:
5.2.1
Byte Write Mode
Once a byte write has been started, it will automatically time itself to completion. A BUSY signal
(MXPSR.7) will be used to detect the end of write operation.
5.2.2
Page Write Mode
The EEPROM is divided into 2 pages and each page contains 64 bytes. The page write allows one to
64 bytes of data to be written into the memory during a single internal programming cycle. Page write
is initiated in the same manner as byte write mode. After the first byte is written, it can then be followed
by one to 63 additional bytes. If a second byte is written within a byte-load cycle time (TBLC) of 150us,
the EEPROM will stay at page load cycle. Additional bytes can then be loaded consecutively. The
page load cycle will be terminated and the internal programming cycle will start if no additional byte is
load within 300us from the last byte be loaded. The address bit6 specify the page address. All bytes
that are loaded to the buffer must have the same page address. The data for page write may be
loaded in any order, the sequential loading is not required.
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