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參數(shù)資料
| 型號： | W78M64VP110SBC |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA156 |
| 封裝： | 13 X 22 MM, PLASTIC, BGA-156 |
| 文件頁數(shù)： | 3/48頁 |
| 文件大?。?/td> | 1548K |
| 代理商： | W78M64VP110SBC |
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11
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W78M64VP-XSBX
October 2008
Rev. 2
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specications without notice.
During a write operation, the system must drive CE# and
WE# to VIL and OE# to VIH when providing an address,
command, and data. Addresses are latched on the last
falling edge of WE# or CE#, while data is latched on the 1st
rising edge of WE# or CE#. An erase operation can erase
one sector, multiple sectors, or the entire device. Table 1
indicate the address space that each sector occupies. The
device address space is divided into uniform 64KW/128KB
sectors. A sector address is the set of address bits required
to uniquely select a sector. ICC2 in “DC Characteristics”
represents the active current specication for the write
mode. “AC Characteristics” contains timing specication
tables and timing diagrams for write operations.
RY/BY#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in progress or
complete. The RY/BY# status is valid after the rising edge of
the nal WE# pulse in the command sequence. Since RY/
BY# is an open-drain output, several RY/BY# pins can be
tied together in parallel with a pull-up resistor to VCC. This
feature allows the host system to detect when data is ready
to be read by simply monitoring the RY/BY# pin, which is a
dedicated output and controlled by CE# (not OE#).
Hardware Reset
The RESET# input provides a hardware method of resetting
the device to reading array data. When RESET# is driven
low for at least a period of tRP (RESET# Pulse Width), the
device immediately terminates any operation in progress,
tristates all outputs, resets the conguration register, and
ignores all read/write commands for the duration of the
RESET# pulse. The device also resets the internal state
machine to reading array data.
To ensure data integrity Program/Erase operations that were
interrupted should be reinitiated once the device is ready to
accept another command sequence.
When RESET# is held at VSS, the device draws VCC reset
current (ICC5). If RESET# is held at VIL, but not at VSS, the
standby current is greater. RESET# may be tied to the
system reset circuitry which enables the system to read the
boot-up rmware from the Flash memory upon a system
reset.
Software Reset
Software reset is part of the command set (see Table 12.1
on page 69) that also returns the device to arrayread mode
and must be used for the following conditions:
1. to exit Autoselect mode
2. when DQ5 goes high during write status operation that
indicates program or erase cycle was not successfully
completed
3. exit sector lock/unlock operation.
4. to return to erase-suspend-read mode if the device was
previously in Erase Suspend mode.
5. after any aborted operations
The following are additional points to consider when using
the reset command:
This command resets the sectors to the read and
address bits are ignored.
Reset commands are ignored during program and
erase operations.
The reset command may be written between the
cycles in a program command sequence before
programming begins (prior to the third cycle). This
resets the sector to which the system was writing to
the read mode.
If the program command sequence is written to a
sector that is in the Erase Suspend mode, writing
the reset command returns that sector to the erase-
suspend-read mode.
The reset command may be written during an
Autoselect command sequence.
If a sector has entered the Autoselect mode while
in the Erase Suspend mode, writing the reset
command returns that sector to the erase-suspend-
read mode.
If DQ1 goes high during a Write Buffer Programming
operation, the system must write the “Write to Buffer
abort Reset” command sequence to RESET the
device to reading array data. The standard RESET
command does not work during this condition.
To exit the unlock bypass mode, the system must
issue a two-cycle unlock bypass reset command
sequence [see Command Denitions for details].
Advanced Sector Protection/
Unprotection
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