參數(shù)資料
型號(hào)： W89C840F
英文描述： LAN NODE CONTROLLER
中文描述： 網(wǎng)絡(luò)節(jié)點(diǎn)控制器
文件頁數(shù)： 14/72頁
文件大?。?/td> 731K
代理商： W89C840F
W89C840F
- 14 -
The data flow of a packet in the receiving path is shown as the following diagram.
data
buffer 1
data
buffer 2
data
buffer 3
data
buffer n
Rx
descriptor 1
Rx
descriptor 2
Rx
descriptor 3
Rx
descriptor n
4 Kbytes FIFO
data
from MAC
receive
DMA
state machine
controls
from MAC
status
control
data
status & control
PCI
master
PCI
PCI slave
As shown the above diagram, the receiving DMA state machine controls the data receiving
processing and the receiving status monitoring. On receiving the data packets, the receiving DMA will start
to move these data from FIFO to the data buffer, pointed by descriptors in the host memory if there is an
available data buffer and the byte count of the data received into the FIFO is larger than or equals to 64
bytes. If the received packet length is less than 64 bytes and runt packet is not accepted, the receiving DMA
will discard this invalid packet and give it a record in the status register. The receiving DMA will start to
move the data in FIFO after the full packet is received if runt packet is accepted. Once a valid packet is
received, the receive DMA will advance the descriptor pointer for the next incoming packet. However, the
current data buffer and the descriptor will be re-used if the current receiving packet is not a valid packet,
i.e. the receive state machine will ignore the previously received packet data in the data buffer. Each
received packet will be treated as a valid packet if it meets the requirement in the bits 3, 4, 5, 6 and 7 of
C18/CNCR register. In some case of the data buffer unavailable temporarily, the incoming packet data from
media will be queued in the FIFO temporarily, meanwhile, the receive DMA will enter suspend state at this
time and a buffer unavailable interrupt will be issued. The receive DMA will start moving the data
whenever the data buffer is available and a receiving operation is demanded, On the other hand, the data
will be lost if the FIFO is overflowed. The receiving status, e.g., the receive descriptor access status, the
receive completion status, the received data byte count, the received packet error status, the received packet
data type, ... and so on., will be written back into the descriptor by the receive DMA when the packet is
received successfully.
During receiving a packet, the receive DMA will release the access right of the descriptor and the
data buffer to the driver immediately after the free byte space of the data buffers pointed by the current
descriptor is counted down to zero and the receive DMA will fetch the next available descriptor for the
current incoming packet. It is known that the LLC layer data is packed into the first 64 bytes of the packet
in most application program. The driver and the upper layer application program can read the protocol
messages carried in the first 64 bytes of the incoming packet when the receive DMA release the descriptor
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W89C841D 制造商:WINBOND 制造商全稱:Winbond 功能描述:3-IN - 1 10/100M FAST ETHERNET CONTROLLER
W89C841F 制造商:WINBOND 制造商全稱:Winbond 功能描述:3-IN - 1 10/100M FAST ETHERNET CONTROLLER
W89C841F/D 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3-IN-1 100BASE-TX/FX & 10BASE-T Ethernet Controller
W89C880F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Hub Controller
W89C92 制造商:WINBOND 制造商全稱:Winbond 功能描述:PCMCIA ETHERNET NETWORK TWISTED PAIR INTERFACE CONTROLLER
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