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參數(shù)資料
| 型號(hào)： | W89C840F |
| 英文描述： | LAN NODE CONTROLLER |
| 中文描述： | 網(wǎng)絡(luò)節(jié)點(diǎn)控制器 |
| 文件頁數(shù)： | 9/72頁 |
| 文件大小： | 731K |
| 代理商： | W89C840F |
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W89C840F
Publication Release Date:April 1997
Revision A1
- 9 -
MTXCLK
I
Transmit clock:
MTXCLK is a continuous uniformed clock source
driven by the external PHY. It provides the timing
reference for the signals MTXEN and MTXD.
MTXCLK should be either 25MHz or 2.5MHz clock.
MTXD[3:0]
O
Transmit Data:
This nibble byte width transmit data bus is synchronized
with MTXCLK. It should be latched by the external
PHY at the rising edge of MTXCLK. MTXD[0] is the
least significant bit.
MTXEN
O
Transmit enable:
It indicates that transmits activity to an external PHY. It
will be synchronized with MTXCLK.
MMDC
O
MII management reference clock.
It is the reference clock of MMDIO. Each data bit will
be latched at the MMDC rising edge.
MMDIO
I/O
MII management data input/output.
This pin is used to transfer the MII control and status
information between PHY and MAC.
MCRS
I
Carrier Sense Signal:
This shall be asserted by PHY device when media is
busy, and deasserted when media is idle. MCRS shall
keep asserted, even at the duration of a collision.
MCOL
I
Collision detected:
This shall be asserted by the PHY device upon detecting
a collision happened over the medium. It will be asserted
and lasted until collision condition wholly vanishes.
MRXDV
I
Received data valid:
This pin is driven by PHY device. It will be asserted
when received data is coming and present, and
deasserted at the end of the frame. MRXDV is
synchronized with MRXCLK from PHY device.
MRXER
I
Received data error:
This pin is driven by PHY device. It indicates a data
conversion error is detected by PHY device. The
assertion of MRXER should be lasted for longer than a
period of MRXCLK. When MRXER asserted,
W89C840F will report a Receive Error detection and a
CRC error
.
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