參數(shù)資料
型號： W89C840F
英文描述： LAN NODE CONTROLLER
中文描述： 網(wǎng)絡(luò)節(jié)點控制器
文件頁數(shù)： 15/72頁
文件大?。?/td> 731K
代理商： W89C840F
W89C840F
Publication Release Date:April 1997
Revision A1
- 15 -
and the data buffer for the current incoming packet, although the current incoming packet is not yet
received completely. The functions of the receive DMA releasing the descriptor and the data buffer which
have been used during receiving a packet allows the software and the hardware to
process the receiving
packet concurrently. This parallel processing of software and the hardware can improve the system
receiving performance significantly.
When the incoming packet is received completely, the receive DMA will write the same copy of the
packet receiving status to the first descriptor and the last descriptor of the current frame respectively. The
receiving status includes the receive completion status, the received byte c
ount, the recei ve error
type and so on.
All of the status is specified in the receive descriptor R00. When the software and
hardware are concurrently processing , the software needs not to go back to read the first descriptor of the
current incoming packet for knowing the receive completed status or other receiving status when it is
processing the last descriptor and the data buffer of the current incoming packet.
I
f there is only one
descriptor needed for the current incoming packet, all of receiving status will be updated in the unique
descriptor.
The W89C840F transmit DMA function performs the data transfer from the host memory through
on-chip PCI bus master into the internal 2 Kbytes transmit FIFO. The transmit DMA state machine will
request the MAC to send out the data in the FIFO onto the MII.
The transmit descriptor is used to set the transmit configuration and to point to the transmit data
buffer locations. Each packet to be transmitted can be described by one or more than one descriptor.
E
ach
descriptor consists of four consecutive long word
s
. The first long word(T00) is for the transmit frame status
register. The T00 describes the descriptor access right control, th
e packet transm tti ng status,
etc.
The second long word(T01) is for the control register
that i s
used to specify the transmission
configuration, including the CRC inhibit control, padding function control,
and
the d
escri ptor
structure control ,
etc. The third long word (T02) is for the first data buffer pointer and the fourth long
word is used as the second data buffer pointer
in the ring structure.
The transmit descriptor list also can be constructed as a ring structure or a chain structure. The
mixed chain and ring structures also are allowed to be constructed. The scheme for constructing the
transmit descriptor list is same as the one for receiving descriptor list, but, each transmit data buffer size is
limited to under 1 Kbytes other than the 2 Kbytes receiving data buffer. In the consequence of the 1 Kbytes
transmit
data buffer, each descri ptor
point to a maximum
of
two
data buffers w th 1 Kbytes
.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W89C841D 制造商:WINBOND 制造商全稱:Winbond 功能描述:3-IN - 1 10/100M FAST ETHERNET CONTROLLER
W89C841F 制造商:WINBOND 制造商全稱:Winbond 功能描述:3-IN - 1 10/100M FAST ETHERNET CONTROLLER
W89C841F/D 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3-IN-1 100BASE-TX/FX & 10BASE-T Ethernet Controller
W89C880F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Hub Controller
W89C92 制造商:WINBOND 制造商全稱:Winbond 功能描述:PCMCIA ETHERNET NETWORK TWISTED PAIR INTERFACE CONTROLLER
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