
W925E/C625
8-bit CID Microcontroller
Revision : A6
-27-
Release Date : 2002/7/2
operating from the on-chip RC oscillator.
This bit is cleared to 0 after a power-on or
reset pin reset and unchanged by WDT reset.
RGSL: RC Oscillator Select. This bit selects the clock source following a resume from Power
Down Mode. Setting this bit allows device operating from RC oscillator when a resume
from Power Down Mode. When this bit is cleared, the device will hold operation until the
crystal oscillator has warmed-up following a resume from Power Down Mode.
This bit is
cleared to 0 after a power-on or reset pin reset and unchanged by WDT reset.
X2OFF: Set to disable sub-oscillator (32KHz oscillator)
X1OFF:Crystal Oscillator Disable. Setting this bit disables the external crystal oscillator. This bit
can only be set to 1 while the micro-controller is operating from the RC oscillator. Clearing
this bit restarts the crystal oscillator, the X1UP (STATUS.4) bit will be set after crystal
oscillator warmed-up has completed.
Note: The bit0 of this SFR must be set to 1.
STATUS REGISTER
(initial=00H)
Bit:
7
6
5
4
3
-
2
-
1
-
0
-
X2UP
HIP
LIP
X1UP
Mnemonic: STATUS
Address: C5h
X2UP:Sub-crystal oscillator warm-up status. When set, this bit indicates the crystal oscillator has
completed the warm-up delay. When X2OFF bit is set, hardware will clear this bit. There
are two options which are selected by option code for warm-up delay, one is 1024 clocks
warm-up delay, other is 65536 clocks warm-up delay.
HIP: High Priority Interrupt Status. When set, it indicates that software is servicing a high priority
interrupt. This bit will be cleared when the program executes the corresponding RETI
instruction.
LIP: Low Priority Interrupt Status. When set, it indicates that software is servicing a low priority
interrupt. This bit will be cleared when the program executes the corresponding RETI
instruction.
X1UP:Crystal Oscillator Warm-up Status. when set, this bit indicates the crystal oscillator has
completed the 65536 clocks warm-up delay. Each time the crystal oscillator is restarted by
exit from power down mode or the X1OFF bit is set, hardware will clear this bit. This bit is
set to 1 after a power-on reset. When this bit is cleared, it prevents software from setting
the XT/RG bit to enable CPU operation from crystal oscillator. There are two options
which is selected by option code for warm-up delay, one is 4096 clocks warm-up delay,
other is 65536 clocks warm-up delay.
FSK TRANSIMT CONTROL REGISTER
(initial=00H)
Bit:
7
6
5
4
-
3
-
2
-
1
0
FTE
FTM
FDS
LO1
LO0
Mnemonic: FSKTC
Address: C6h
FTE: FSK transmit Enable; Enable:1, Disable=0
FTM: FSK signal Standard; Bellcore:1, V.23=0
FDS: FSK data sending status
LO0, LO1: FSK transmit level option
FSK output level
LO1
LO0