參數(shù)資料
型號(hào)： WEDPNF8M722V-1015BC
元件分類(lèi)： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA275
封裝： 35 X 25 MM, PLASTIC, BGA-275
文件頁(yè)數(shù)： 10/41頁(yè)
文件大?。?/td> 522K
代理商： WEDPNF8M722V-1015BC
18
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPNF8M722V-XBX
AUTOSELECT MODE
The autoselect mode provides sector protection verification, through
identifier codes input codes output on FD7-0. This mode is prima-
rily intended for programming equipment to automatically match
a device to be programmed with its corresponding programming
algorithm. However, the autoselect codes can also be accessed
in-system through the command register.
When using programming equipment, the autoselect mode re-
quires VID (11.5V to 12.5V) on address pin FA9. Address pins FA6,
FA1, and FA0 must be as shown in Table 6. In addition, when
verifying sector protection, the sector address must appear on the
appropriate highest order address bits (see Table 5). Table 6
shows the remaining address bits that are “don't care.” When all
necessary bits have been set as required, the programming equip-
ment may then read the corresponding identifier code on FD7-0 or
FD23-16 .
To access the autoselect codes in-system, the host system can
issue the autoselect command via the command register, as
shown in Table 7. This method does not require VID. See “Com-
mand Definitions” for details on using the autoselect mode.
SECTOR PROTECTION/UNPROTECTION
The hardware sector protection feature disables both program
and erase operations in any sector. The hardware sector unprotection
feature re-enables both program and erase operations in previ-
ously protected sectors.
The device is shipped with all sectors unprotected.
It is possible to determine whether a sector is protected or
unprotected. See “Autoselect Mode” for details.
This operation requires VID on the RST pin only, and can be
implemented either in-system or via programming equipment. The
timing diagram is shown in figure 18. This method uses standard
microprocessor bus cycle timing. For sector unprotect, all unpro-
tected sectors must first be protected prior to the first sector
unprotect write cycle.
TABLE 6 - AUTOSELECT CODES (HIGH VOLTAGE METHOD)
Description
FCS1-2
FOE
FWE
FA18
-12
FA11-10
FA9
FA8-7
FA6
FA5-2
FA1
FA0
FD7-0
FD23-16
Sector Protection
LL
H
SA
X
VID
XL
X
H
L
Verificaton
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don't Care
01h
(protected)
00h
(unprotected)
TEMPORARY SECTOR UNPROTECT
This feature allows temporary unprotection of previously pro-
tected sector groups to change data-in system. The Sector Unprotect
mode is activated by setting the RST pin to VID. During this mode,
formerly protected sector can be programmed or erased by select-
ing the sector addresses. Once VID is removed from the RST pin,
all the previously protected sector groups will be protected again.
Figure 16 shows the algorithm and the timing diagram is shown in
Figure 17, for this feature.
HARDWARE DATA PROTECTION
The command sequence requirement of unlock cycles for pro-
gramming or erasing provides data protection against inadvertent
writes (refer to Table 7 for command definitions). In addition, the
following hardware data protection measures prevent accidental
erasure or programming, which might otherwise be caused by
spurious system level signals during Vcc power-up and power-
down transitions, or from system noise.
Low Vcc Write Inhibit
When Vcc is less than VLKO, the device does not accept any write
cycles. This protects data during Vcc power-up and power-down.
The command register and all internal program/erase circuits are
disabled, and the device resets. Subsequent writes are ignored
until Vcc is greater than VLKO. The system must provide the proper
signals to the control pins to prevent unintentional writes when
Vcc is greater than VLKO.
Write Pulse "Glitch" Protection
Noise pulses of less than 5ns (typical) on FOE, FCS1-2 or FWE do
not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of FOE = VIL,
FCS1-2 = VIH or FWE = VIH. To initiate a write cycle, FCS1-2 and
FWE must be a logical zero while FOE is a logical one.
Power-Up Write Inhibit
If FWE = FCS1-2 = VIL and FOE = VIH during power up, the device
does not accept commands on the rising edge of FWE. The internal
state machine is automatically reset to reading array data on
power-up.
01h
(protected)
00h
(unprotected)
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WEDPNF8M722V-1015BI 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package
WEDPNF8M722V-1015BM 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package
WEDPNF8M722V-1210BC 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package
WEDPNF8M722V-1210BI 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package
WEDPNF8M722V-1210BM 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package
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