
WM8170
Product Preview Rev 1.0
WOLFSON MICROELECTRONICS LTD
PP Rev 1.0 March 2000
17
PROGRAMMABLE GAIN AMPLIFIER
The WM8170 contains a Programmable Gain Amplifier (PGA), which precedes the analogue-to-
digital converter (ADC). The gain of the PGA is set digitally via the management interface to a level
which delivers the maximum signal to the input of the ADC without it over ranging, and thus obtaining
the maximum dynamic range from the ADC.
The gain control on the WM8170 is separated into two sections, a programmable gain section, and a
fixed gain section. The programmable gain section is controlled via an 8-bit word written by the
management interface, and has a typical range of between 0dB and 28dB. The gain response of the
programmable gain section is linear on a logarithmic scale. This means that each LSB increase (or
decrease) of digital gain setting represents an equal fraction of a dB (typically 0.11dB) of actual gain
increase (or decrease).
There is also a fixed gain section, which is programmable to be either 0dB or 6dB. Setting the
TIMES2 control bit via the management interface enables this additional gain.
Figure 13 shows the typical WM8170 gain response with and without the additional 6dB.
63
127
191
255
6
28
34
TMES2=0
PGA CODE
PGA GAIN
(dB)
0
TMES2=1
Figure 13 Graph of typical WM8170 Gain Response
REFERENCE VOLTAGES
All references used on the WM8170 are derived from an internal bandgap reference voltage. The
ADC uses two reference voltages, VRT and VRB. The Sample/Hold and PGA use a midrail voltage
reference, VMID. The voltage for Reset Level Clamp, VCLP, can be selected to be equal to VRT,
VRB or VMID. These four voltages are buffered on-chip and are each available at output pins. Each
of these pins should be carefully decoupled with capacitors of the type and size detailed in the
Recommended External Components section.
The voltage difference between VRT and VRB can be programmed, in order to accommodate
different input signal ranges, to two values via the management interface. The WM8170 default
condition is VRT-VRB typically 0.5V but can be increased to 0.75V by setting the V375 control bit.
Due to the nature of the ADC design, the difference between VRT and VRB is typically half the
maximum input signal which the ADC can convert successfully, i.e. if VRT-VRB is 0.75V, then the
ADC can accommodate an input signal after the PGA of greater than 1.5V.