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參數(shù)資料
| 型號(hào)： | WV3EG128M72EFSR262D3MG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封裝： | ROHS COMPLIANT, DIMM-184 |
| 文件頁(yè)數(shù)： | 13/13頁(yè) |
| 文件大?。?/td> | 382K |
| 代理商： | WV3EG128M72EFSR262D3MG |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
March 2005
Rev. 0
ADVANCED
WV3EG128M72EFSR-D3
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS (continued)
Notes 1-5, 7; notes appear following parameter tables; 0°C ≤ TA ≤ +70°C; VCC = +2.5V ±0.2V, VCCQ = +2.5V ±0.2V
AC Characteristics
335
262
265
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Units
Notes
ACTIVE to READ or WRITE delay
tRCD
18
20
ns
PRECHARGE command period
tRP
18
20
ns
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
19
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
ACTIVE bank a to ACTIVE bank b command
tRRD
12
15
ns
DQS write preamble
tWPRE
0.25
tCK
DQS write preamble setup time
tWPRES
0
ns
10,11
DQS write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
9
Write recovery time
tWR
15
ns
Internal WRITE to READ command delay
tWTR
111tCK
Average periodic refresh interval
tREFI
7.8
μs12
Exit SELF REFRESH to non-READ command
tXSNR
75
ns
Exit SELF REFRESH to READ command
tXSRD
200
tCK
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WV3EG128M72EFSR262D3SF | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA |
| WV3EG128M72EFSR262D3SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA |
| WV3EG128M72EFSR265D3MF | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA |
| WV3EG128M72EFSR265D3MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA |
| WV3EG128M72EFSR265D3SF | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA |
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