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參數(shù)資料
| 型號： | X1228 |
| 廠商： | Intersil Corporation |
| 英文描述： | EPD TVS Diode Array for ESD and Latch-Up Protection |
| 中文描述： | 實時時鐘/日歷/ CPU，具有EEPROM的監(jiān) |
| 文件頁數(shù)： | 13/31頁 |
| 文件大?。?/td> | 569K |
| 代理商： | X1228 |
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X1228
REV 1.3 3/24/04
Characteristics subject to change without notice.
13 of 31
www.xicor.com
STATUS REGISTER (SR)
The Status Register is located in the CCR memory
map area at address 003Fh. This is a volatile register
only and is used to control the WEL and RWEL write
enable latches, read two power status and two alarm
bits. This register is separate from both the array and
the Clock/Control Registers (CCR).
Table 2. Status Register (SR)
BAT: Battery Supply—Volatile
This bit set to “1” indicates that the device is operating
from V
BACK
, not V
CC
. It is a read-only bit and is set/
reset by hardware (X1228 internally). Once the device
begins operating from V
CC
, the device sets this bit to
“0”.
AL1, AL0: Alarm bits—Volatile
These bits announce if either alarm 0 or alarm 1 match
the real time clock. If there is a match, the respective
bit is set to ‘1’. The falling edge of the last data bit in a
SR Read operation resets the flags. Note: Only the AL
bits that are set when an SR read starts will be reset.
An alarm bit that is set by an alarm occurring during an
SR read operation will remain set after the read opera-
tion is complete.
RWEL: Register Write Enable Latch—Volatile
This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to “1” prior
to any writes to the Clock/Control Registers. Writes to
RWEL bit do not cause a nonvolatile write cycle, so the
device is ready for the next operation immediately after
the stop condition. A write to the CCR requires both
the RWEL and WEL bits to be set in a specific
sequence.
WEL: Write Enable Latch—Volatile
The WEL bit controls the access to the CCR and mem-
ory array during a write operation. This bit is a volatile
latch that powers up in the LOW (disabled) state. While
the WEL bit is LOW, writes to the CCR or any array
address will be ignored (no acknowledge will be issued
after the Data Byte). The WEL bit is set by writing a “1”
to the WEL bit and zeroes to the other bits of the Sta-
tus Register. Once set, WEL remains set until either
reset to 0 (by writing a “0” to the WEL bit and zeroes to
the other bits of the Status Register) or until the part
powers up again. Writes to WEL bit do not cause a
nonvolatile write cycle, so the device is ready for the
next operation immediately after the stop condition.
RTCF: Real Time Clock Fail Bit—Volatile
This bit is set to a ‘1’ after a total power failure. This is a
read only bit that is set by hardware (X1228 internally)
when the device powers up after having lost all power
to the device. The bit is set regardless of whether V
CC
or V
BACK
is applied first. The loss of only one of the
supplies does not result in setting the RTCF bit. The
first valid write to the RTC after a complete power fail-
ure (writing one byte is sufficient) resets the RTCF bit
to ‘0’.
Unused Bits:
This device does not use bits 3 or 4 in the SR, but must
have a zero in these bit positions. The Data Byte out-
put during a SR read will contain zeros in these bit
locations.
CONTROL REGISTERS
The Control Bits and Registers, described under this
section, are nonvolatile.
Block Protect Bits—BP2, BP1, BP0
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to a
protected block of memory is ignored. The block protect
bits will prevent write operations to one of eight segments
of the array. The partitions are described in Table 3 .
Table 3. Block Protect Bits
Watchdog Timer Control Bits—WD1, WD0
The bits WD1 and WD0 control the period of the
Watchdog Timer. See Table 4 for options.
Addr
003Fh
Default
7
6
5
4
0
0
3
0
0
2
1
0
BAT
0
AL1
0
AL0
0
RWEL
0
WEL
0
RTCF
1
B
B
B
Protected Addresses
X1228
None
180h – 1FFh
100h – 1FFh
000h – 1FFh
000h – 03Fh
000h – 07Fh
000h – 0FFh
000h – 1FFh
Array Lock
None (Default)
Upper 1/4
Upper 1/2
Full Array
First Page
First 2 pgs
First 4 pgs
First 8 pgs
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
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