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參數(shù)資料
| 型號： | X1228 |
| 廠商： | Intersil Corporation |
| 英文描述： | EPD TVS Diode Array for ESD and Latch-Up Protection |
| 中文描述： | 實時時鐘/日歷/ CPU，具有EEPROM的監(jiān) |
| 文件頁數(shù)： | 17/31頁 |
| 文件大?。?/td> | 569K |
| 代理商： | X1228 |
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X1228
REV 1.3 3/24/04
Characteristics subject to change without notice.
17 of 31
www.xicor.com
Figure 5. Set V
TRIP
Level Sequence (V
CC
= desired V
TRIP
value)
Resetting the V
TRIP
Voltage
This procedure is used to set the V
TRIP
voltage level. For example, if the current V
TRIP
is 4.4V
and the new V
TRIP
must be 4.0V, then the V
TRIP
must
be reset. When V
TRIP
is reset, the new V
TRIP
is some-
thing less than 1.7V. This procedure must be used to
set the voltage to a lower value.
To reset the new V
TRIP
voltage, apply more than 5.5V
to the V
CC
pin and tie the RESET pin to the
programming voltage V
P
. Then write 00h to address
03h. The stop bit of a valid write operation initiates the
V
TRIP
programming sequence. Bring RESET to V
CC
to
complete the operation.
Note:
this operation takes up
to 10 milliseconds to complete and also writes 00h to
address 03h of the EEPROM array.
For best accuracy in setting V
TRIP
, it is advised that the
following sequence be used.
1.Program V
TRIP
as above.
2.Measure resulting V
TRIP
by measuring the V
CC
value where a RESET occurs. Calculate Delta =
(Desired – Measured) V
TRIP
value.
3.Perform a V
TRIP
program using the following formula
to set the voltage of the RESET pin:
V
RESET
= (Desired Value – Delta) + 0.025V
Figure 6. Reset V
TRIP
Level Sequence
SCL
SDA
01h
RESET
V
P
= 15V
00h
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
AEh
00h
V
CC
V
CC
Note:
BP0, BP1, BP2 must be disabled.
0 1 2 3 4 5 6 7
SCL
SDA
AEh
0 1 2 3 4 5 6 7
03h
RESET
V
P
= 15V
00h
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
00h
V
CC
V
CC
Note:
BP0, BP1, BP2 must be disabled.
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