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| 型號： | X1228S14I-4.5A |
| 廠商： | INTERSIL CORP |
| 元件分類： | XO, clock |
| 英文描述： | 15V 300W SOT23 TRANSORB-DUAL-SINGL''ENDED |
| 中文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO14 |
| 封裝： | PLASTIC, SOIC-14 |
| 文件頁數(shù)： | 18/31頁 |
| 文件大?。?/td> | 569K |
| 代理商： | X1228S14I-4.5A |
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X1228
REV 1.3 3/24/04
Characteristics subject to change without notice.
18 of 31
www.xicor.com
SERIAL COMMUNICATION
Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data trans-
fers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this family
operate as slaves in all applications.
Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 7.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met. See
Figure 8.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the Standby power mode after a
read sequence. A stop condition can only be issued
after the transmitting device has released the bus. See
Figure 8.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle, the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 9.
The device will respond with an acknowledge after rec-
ognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave
Address Byte. If a write operation is selected, the
device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for:
– The Slave Address Byte when the Device Identifier
and/or Select bits are incorrect
– All Data Bytes of a write when the WEL in the Write
Protect Register is LOW
– The 2nd Data Byte of a Status Register Write Opera-
tion (only 1 data byte is allowed)
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
Figure 7. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
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