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參數(shù)資料
| 型號： | X1228S14I-4.5A |
| 廠商： | INTERSIL CORP |
| 元件分類： | XO, clock |
| 英文描述： | 15V 300W SOT23 TRANSORB-DUAL-SINGL''ENDED |
| 中文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO14 |
| 封裝： | PLASTIC, SOIC-14 |
| 文件頁數(shù)： | 22/31頁 |
| 文件大?。?/td> | 569K |
| 代理商： | X1228S14I-4.5A |
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X1228
REV 1.3 3/24/04
Characteristics subject to change without notice.
22 of 31
www.xicor.com
Acknowledge Polling
Disabling of the inputs during nonvolatile write cycles
can be used to take advantage of the typical 5mS write
cycle time. Once the stop condition is issued to indi-
cate the end of the master’s byte load operation, the
X1228 initiates the internal nonvolatile write cycle.
Acknowledge polling can begin immediately. To do this,
the master issues a start condition followed by the
Memory Array Slave Address Byte for a write or read
operation (AEh or AFh). If the X1228 is still busy with
the nonvolatile write cycle then no ACK will be
returned. When the X1228 has completed the write
operation, an ACK is returned and the host can pro-
ceed with the read or write operation. Refer to the flow
chart in Figure 15. Note: Do not use the CCR Salve
byte (DEh or DFh) for Acknowledge Polling.
Read Operations
There are three basic read operations: Current
Address Read, Random Read, and Sequential Read.
Current Address Read
Internally the X1228 contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power up, the sixteen bit
address is initialized to 0h. In this way, a current
address read immediately after the power on reset can
download the entire contents of memory starting at the
first location.Upon receipt of the Slave Address Byte
with the R/W bit set to one, the X1228 issues an
acknowledge, then transmits eight data bits. The mas-
ter terminates the read operation by not responding
with an acknowledge during the ninth clock and issuing
a stop condition. Refer to Figure 14 for the address,
acknowledge, and data transfer sequence.
Figure 15. Acknowledge Polling Sequence
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Figure 14. Current Address Read Sequence
ACK
returned
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue STOP
Issue START
NO
YES
Issue STOP
NO
Continue normal
Read or Write
command
sequence
PROCEED
YES
nonvolatile write
Cycle complete. Continue
command sequence
Issue Memory Array Slave
Address Byte
AFh (Read) or AEh (Write)
S
t
a
r
t
S
t
o
p
Slave
Address
Data
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
1
1
1
1
1
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