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參數(shù)資料
| 型號： | X1228V14Z-2.7A |
| 廠商： | INTERSIL CORP |
| 元件分類： | XO, clock |
| 英文描述： | EXT. DISTANCE DATA CABLE 25 CO |
| 中文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO14 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MO-153AC, TSSOP-14 |
| 文件頁數(shù)： | 19/31頁 |
| 文件大?。?/td> | 569K |
| 代理商： | X1228V14Z-2.7A |
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X1228
REV 1.3 3/24/04
Characteristics subject to change without notice.
19 of 31
www.xicor.com
Figure 8. Valid Start and Stop Conditions
Figure 9. Acknowledge Response From Receiver
DEVICE ADDRESSING
Following a start condition, the master must output a
Slave Address Byte. The first four bits of the Slave
Address Byte specify access to either the EEPROM
array or to the CCR. Slave bits ‘1010’ access the
EEPROM array. Slave bits ‘1101’ access the CCR.
When shipped from the factory, EEPROM array is
UNDEFINED, and should be programmed by the cus-
tomer to a known state.
Bit 3 through Bit 1 of the slave byte specify the device
select bits. These are set to ‘111’.
The last bit of the Slave Address Byte defines the oper-
ation to be performed. When this R/W bit is a one, then
a read operation is selected. A zero selects a write
operation. Refer to Figure 10.
After loading the entire Slave Address Byte from the
SDA bus, the X1228 compares the device identifier
and device select bits with ‘1010111’ or ‘1101111’.
Upon a correct compare, the device outputs an
acknowledge on the SDA line.
Following the Slave Byte is a two byte word address.
The word address is either supplied by the master
device or obtained from an internal counter. On power
up the internal address counter is set to address 0h, so
a current address read of the EEPROM array starts at
address 0. When required, as part of a random read,
the master must supply the 2 Word Address Bytes as
shown in Figure 10.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in the
“read” section. That is if the random read is from the
array the slave byte must be 1010111x in both
instances. Similarly, for a random read of the Clock/
Control Registers, the slave byte must be 1101111x in
both places.
SCL
SDA
Start
Stop
SCL from
Master
Data Output
from Transmitter
Data Output
from Receiver
8
1
9
Start
Acknowledge
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| X1228V14Z-4.5A | 功能描述:IC RTC/CAL/CPU SUP EE 14-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 實時時鐘 系列:- 產(chǎn)品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:時鐘/日歷 特點:警報器，閏年，SRAM 存儲容量:- 時間格式:HH:MM:SS（12/24 小時） 數(shù)據(jù)格式:YY-MM-DD-dd 接口:SPI 電源電壓:2 V ~ 5.5 V 電壓 - 電源，電池:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤 供應商設備封裝:8-TDFN EP 包裝:管件 |
| X1228ZY WAF | 制造商:Intersil Corporation 功能描述: |
| X122K | 制造商:IQD Frequency Products 功能描述:CRYSTAL OSCILLATOR 12.288000MHZ |
| X122-SERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| X123-133.33M | 制造商:CONNOR-WINFIELD 制造商全稱:Connor-Winfield Corporation 功能描述:5.0x7.0mm Surface Mount LVCMOS Clock Oscillator Series |
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