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參數(shù)資料
| 型號(hào)： | X25097M-2.7 |
| 英文描述： | 2-Phase Dual Synchronous PWM Controller with Oscillator Synchronization and Pre-Bias Startup; A IR3621 packaged in a 28-Pin TSSOP on Tape and Reel |
| 中文描述： | SPI串行EEPROM |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 136K |
| 代理商： | X25097M-2.7 |
FORNEWDESGN
bits of the address are used and bits [15:10] are speci-
fied to be zeroes. This is minimally a thirty-two clock
operation. CS must go LOW and remain LOW for the
duration of the operation. The host may continue to
write up to 16 bytes of data to the X25097. The only
X25097
Characteristics subject to change without notice.
3 of 14
REV 1.1 9/8/00
www.xicor.com
The X25097 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in
on the rising edge of SCK. CS must be LOW and the
WP input must be HIGH during the entire operation.
Table 1
contains a list of the instructions and their
opcodes. All instructions, addresses and data are
transferred MSB first.
Data input is sampled on the first rising edge of SCK
after CS goes LOW. SCK is static, allowing the user to
stop the clock, and then start it again to resume opera-
tions where left off.
Write Enable Latch
The X25097 contains a “Write Enable” latch. This latch
must be SET before a write operation is initiated. The
WREN instruction will set the latch and the WRDI
instruction will reset the latch (Figure 4). This latch is
automatically reset upon a power-up condition and
after the completion of a byte or page write cycle.
IDLock Memory
Xicor’s IDLock Memory provides a flexible mechanism
to store and lock system ID and parametric informa-
tion. There are seven distinct IDLock Memory areas
within the array which vary in size from one page to as
much as half of the entire array. These areas and asso-
ciated address ranges are IDLocked by writing the
appropriate two byte IDLock instruction to the device
as described in Table 1 and Figure 7. Once an IDLock
instruction has been completed, that IDLock setup is
held in a nonvolatile Status Register (Figure 1) until the
next IDLock instruction is issued. The sections of the
memory array that are IDLocked can be read (but not
written) until IDLock Protection is removed or changed.
Table 1. Status Register/IDLock Protection Byte
Note:
Bits [7:3] specified to be “0’s”
Clock and Data Timing
Data input on the SI line is latched on the rising edge
of SCK. Data is output on the SO line by the falling
edge of SCK.
Read Sequence
When reading from the EEPROM memory array, CS is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25097, followed by
the 16-bit address, of which the last 10 bits are used
(bits [15:10] specified to be zeroes). After the READ
opcode and address are sent, the data stored in the
memory at the selected address is shifted out on the SO
line. The data stored in memory at the next address can
be read sequentially by continuing to provide clock
pulses. The address is automatically incremented to
the next higher address after each byte of data is
shifted out. When the highest address is reached
(03FFh), the address counter rolls over to address
0000h, allowing the read cycle to be continued indefi-
nitely. The read operation is terminated by taking CS
HIGH. Refer to the Read Operation Sequence illus-
trated in Figure 2.
Read Status Operation
If there is not a nonvolatile write in progress, the Read
Status instruction returns the ID Lock byte from the
Status Register which contains the ID Lock bits IDL2-
IDL0 (Figure 1). The ID Lock bits define the ID Lock
condition (Figure 1/Table1). The other bits are reserved
and will return ‘0’ when read. See Figure 3.
If a nonvolatile write is in progress, the Read Status
Instruction returns a HIGH on SO. When the nonvola-
tile write cycle is completed, the status register data is
read out.
Clocking SCK is valid during a nonvolatile write in
progress, but is not necessary. If the SCK line is
clocked, the pointer to the status register is also
clocked, even though the SO pin shows the status of
the nonvolatile write operation (See Figure 3).
Write Sequence
Prior to any attempt to write data into the X25097, the
“Write Enable” latch must first be set by issuing the
WREN instruction (See Table 1 and Figure 4). CS is
first taken LOW. Then the WREN instruction is clocked
into the X25097. After all eight bits of the instruction
are transmitted, CS must then be taken HIGH. If the
user continues the write operation without taking CS
HIGH after issuing the WREN instruction, the write
operation will be ignored.
To write data to the EEPROM memory array, the user
then issues the WRITE instruction, followed by the 16
7
0
6
0
5
0
4
0
3
0
2
1
0
IDL2
IDL1
IDL0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X25097MI-2.7 | 2-Phase Dual Synchronous PWM Controller with Oscillator Synchronization and Pre-Bias Startup; Similar to IR3621M with Lead-Free packaging. |
| X25097V-1.8 | 5MHz Low Power SPI Serial E 2 PROM with IDLock TM Memory |
| X25097PI-1.8 | XTAL MTL T/H HC49/U |
| X25097PI-2.7 | XTAL CER SMT 7X5 2PAD |
| X25097VI-1.8 | 5MHz Low Power SPI Serial E 2 PROM with IDLock TM Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X25097MI-2.7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM |
| X25097P | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:5MHz Low Power SPI Serial E2PROM with IDLockTM Memory |
| X25097P-1.8 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:5MHz Low Power SPI Serial E2PROM with IDLockTM Memory |
| X25097P-2.7 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:5MHz Low Power SPI Serial E2PROM with IDLockTM Memory |
| X25097PG | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:5MHz Low Power SPI Serial E2PROM with IDLockTM Memory |
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