參數(shù)資料
型號(hào): X25097M-2.7
英文描述: 2-Phase Dual Synchronous PWM Controller with Oscillator Synchronization and Pre-Bias Startup; A IR3621 packaged in a 28-Pin TSSOP on Tape and Reel
中文描述: SPI串行EEPROM
文件頁(yè)數(shù): 4/14頁(yè)
文件大小: 136K
代理商: X25097M-2.7
FORNEWDESGN
Note:
*Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first.
X25097
Characteristics subject to change without notice.
4 of 14
REV 1.1 9/8/00
www.xicor.com
restriction is the 16 bytes must reside on the same
page. If the address counter reaches the end of the
page and the clock continues, the counter will “roll
over” to the first address of the page and overwrite any
data that may have been previously written.
For a byte or page write operation to be completed, CS
can only be brought HIGH after bit 0 of the last data
byte to be written is clocked in. If it is brought HIGH at
any other time, the write operation will not be com-
pleted. Refer to Figures 5 and 6 for detailed illustration
of the write sequences and time frames in which CS
going HIGH are valid.
IDLock Operation
Prior to any attempt to perform an IDLock Operation,
the WREN instruction must first be issued. This instruc-
tion sets the “Write Enable” latch and allows the part to
respond to an IDLock sequence (Figure 7). The IDLock
instruction follows and consists of one command byte
followed by one IDLock byte (See Figure 1). This byte
contains the IDLock bits IDL2-IDL0. The rest of the bits
[7:3] are unused and must be written as zeroes. Bring-
ing CS HIGH after the two byte IDLock instruction, ini-
tiates a nonvolatile write to the Status Register. Writing
more than one byte to the Status Register will over-
write the previously written IDLock byte. See Table 1.
Operational Notes
The X25097 powers up in the following state:
– The device is in the low power, standby state.
– A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
– SO pin is at high impedance.
– The “Write Enable” latch is reset.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The “Write Enable” latch is reset upon power-up.
– A WREN instruction must be issued to set the “Write
Enable” latch.
– CS must come HIGH at the proper clock count in
order to start a write cycle.
Table 2. Instruction Set and Block Lock Protection Byte Definition
Instruction Format*
0000 0110
0000 0100
0000 0001
Instruction Name and Operation
WREN: Set the write enable latch (write enable operation)
WRDI: Reset the write enable latch (write disable operation)
IDLock Instruction—followed by:
IDLock Byte: (See Figure 1)
0000 0000 --->NO IDLock: 00h-00h>None of the Array
0000 0001 --->IDLock Q1: 0000h-00FFh--->Lower Quadrant (Q1)
0000 0010 --->IDLock Q2: 0100h-01FFh--->Q2
0000 0011 --->IDLock Q3: 0200h-02FFh--->Q3
0000 0100 --->IDLock Q4: 0300h-03FFh--->Upper Quadrant (Q4)
0000 0101 --->IDLock H1: 0000h-01FFh--->Lower Half of the Array (H1)
0000 0110 --->IDLock P0: 0000h-000Fh--->Lower Page (P0)
0000 0111 --->IDLock Pn: 03F0h-03FFh--->Upper Page (Pn)
READ STATUS: Reads IDLock & write in progress status on SO pin
WRITE: Write operation followed by address and data
READ: Read operation followed by address
0000 0101
0000 0010
0000 0011
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