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參數(shù)資料
| 型號： | X28HC64PZ-90 |
| 廠商： | INTERSIL CORP |
| 元件分類： | DRAM |
| 英文描述： | 5 Volt, Byte Alterable EEPROM |
| 中文描述： | 8K X 8 EEPROM 5V, 90 ns, PDIP28 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-011AB, DIP-28 |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 265K |
| 代理商： | X28HC64PZ-90 |
5
FN8109.1
June 7, 2006
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE
LOW. The read operation is terminated by either CE or
OE returning HIGH. This two line control architecture
eliminates bus contention in a system environment.
The data bus will be in a high impedance state when
either OE or CE is HIGH.
Write
Write operations are initiated when both CE and WE
are LOW and OE is HIGH. The X28HC64 supports
both a CE and WE controlled write cycle. That is, the
address is latched by the falling edge of either CE or
WE, whichever occurs last. Similarly, the data is
latched internally by the rising edge of either CE or
WE, whichever occurs first. A byte write operation,
once initiated, will automatically continue to comple-
tion, typically within 2ms.
Page Write Operation
The page write feature of the X28HC64 allows the
entire memory to be written in 0.25 seconds. Page write
allows two to sixty-four bytes of data to be consecutively
written to the X28HC64 prior to the commencement of
the internal programming cycle. The host can fetch data
from another device within the system during a page
write operation (change the source address), but the
page address (A
6
through A
12
) for each subsequent
valid write cycle to the part during this operation must
be the same as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the
host can write an additional one to sixty-three bytes in
the same manner. Each successive byte load cycle,
started by the WE HIGH to LOW transition, must begin
within 100μs of the falling edge of the preceding WE. If
a subsequent WE HIGH to LOW transition is not
detected within 100μs, the internal automatic program-
ming cycle will commence. There is no page write win-
dow limitation. Effectively the page write window is
infinitely wide, so long as the host continues to access
the device within the byte load cycle time of 100μs.
Write Operation Status Bits
The X28HC64 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Figure 1. Status Bit Assignment
DATA Polling (I/O
7
)
The X28HC64 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a sim-
ple bit test operation to determine the status of the
X28HC64, eliminating additional interrupt inputs or
external hardware. During the internal programming
cycle, any attempt to read the last byte written will pro-
duce the complement of that data on I/O
7
(i.e. write
data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O
7
will reflect true data.
Toggle Bit (I/O
6
)
The X28HC64 also provides another method for deter-
mining when the internal write cycle is complete. Dur-
ing the internal programming cycle I/O
6
will toggle
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
5
TB
DP
4
3
2
1
0
I/O
Reserved
Toggle Bit
DATA Polling
X28HC64
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| X28HC64S-12 | 功能描述:電可擦除可編程只讀存儲器 8K X 8 電可擦除可編程只讀存儲器,HIGH SPEED,CMOS,C.TEMP,120NS RoHS:否 制造商:Intersil 存儲容量: 組織: 數(shù)據(jù)保留: 最大時鐘頻率: 最大工作電流: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體: |
| X28HC64S-12T1 | 功能描述:電可擦除可編程只讀存儲器 8K X 8,CMOS 電可擦除可編程只讀存儲器,SDP,28 SOIC,COM.,120NS, T & R RoHS:否 制造商:Intersil 存儲容量: 組織: 數(shù)據(jù)保留: 最大時鐘頻率: 最大工作電流: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體: |
| X28HC64S-12T2 | 功能描述:電可擦除可編程只讀存儲器 8K X 8 電可擦除可編程只讀存儲器,HIGH SPEED,CMOS,C.TEMP,120NS RoHS:否 制造商:Intersil 存儲容量: 組織: 數(shù)據(jù)保留: 最大時鐘頻率: 最大工作電流: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體: |
| X28HC64S-12T4 | 制造商:Intersil Corporation 功能描述:EEPROM PARALLEL 64KBIT 8KX8 5V 28SOIC W - Tape and Reel |
| X28HC64S-12T5 | 制造商:Intersil Corporation 功能描述:EEPROM PARALLEL 64KBIT 8KX8 5V 28SOIC W - Tape and Reel |
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