參數(shù)資料
型號(hào): X3100V
英文描述: QFN,GREEN,IND TEMP,T&R(ARM)
中文描述: 電池管理
文件頁(yè)數(shù): 15/40頁(yè)
文件大小: 249K
代理商: X3100V
X3100/X3101 – Preliminary Information
Characteristics subject to change without notice.
15 of 40
REV 1.1.8 12/10/02
www.xicor.com
Over-discharge Protection
If V
CELL
< V
UV
, for a time exceeding T
UV
, the cells are
said to be in a over-discharge state (Figure 6). In this
instance, the X3100 and X3101 automatically switch
the discharge FET OFF (UVP/OCP=Vcc), and then
enter sleep mode.
The over-discharge (under-voltage) value, V
UV
, can be
selected from the values shown in Table 5 by setting
bits VUV1, VUV0 in the configuration register. These
bits are set using the WCFIG command. Once in the
sleep mode, the following steps must occur before the
X3100 or X3101 allows the battery cells to discharge:
– The X3100 and X3101 must wake from sleep mode
(see section “Voltage Regulator” on page 21).
– The charge FET must be switched ON by the micro-
controller (OVP/LMON=V
SS
), via the control register
(see section “Control Register Functionality” on page
10).
– All battery cells must satisfy the condition: V
CELL
>
V
UVR
for a time exceeding T
UVR
.
– The discharge FET must be switched ON by the micro-
controller (UVP/OCP=V
SS
), via the control register
(see section “Control Register Functionality” on page
10)
The times T
UV
/T
UVR
are varied using a capacitor (C
UV
)
connected between pin UVT and GND (Table 13). The
delay T
UV
that results from a particular capacitance C
UV
,
can be approximated by the following linear equation:
T
UV
(s)
10 x C
UV
(μF)
T
UVR
(ms)
70 x C
UV
(μF)
Sleep Mode
The X3100 or X3101 can enter sleep mode in two
ways:
i) The device enters the over-discharge protection mode.
ii) The user sends the device into sleep mode using the
control register.
A sleep mode can be induced by the user, by setting
the SLP bit in the control register (Table 13) using the
WCNTR Instruction.
In sleep mode, power to all internal circuitry is switched
off, minimizing the current drawn by the device to 1μA
(max). In this state, the discharge FET and the charge
FET are switched OFF (OVP/LMON=V
CC
and UVP/
OCP=V
CC
), and the 5VDC regulated output (V
RGO
) is
0V. Control of UVP/OCP and OVP/LMON via bits UVPC
and OVPC in the control register is also prohibited.
The device returns from sleep mode when V
CC
V
SLR
.
(e.g. when the battery terminals are connected to a
battery charger). In this case, the X3100 or the X3101
restores the 5VDC regulated output (section “Voltage
Regulator” on page 21), and communication via the SPI
port resumes.
If the Cell Charge Enable function is enabled when V
CC
rises above V
SLR
, the X3100 and X3101 internally
verifies that the individual battery cell voltages (V
CELL
)
are larger than the
cell charge enable voltage (V
CE
)
before allowing the FETs to be turned on.
The value
of V
CE
is selected by using the WCFIG command to set
bits VCE1–VCE0 in the configuration register.
Only if the condition “
V
CELL
>
V
CE
” is satisfied can
the state of
charge and discharge FETs be changed
via the control register
.
Otherwise, if V
CELL
<
V
CE
for
any battery cell then both the Charge FET and the
discharge FET are OFF (OVP/LMON=Vcc and UVP/
OCP=V
CC
). Thus both charge and discharge of the
battery cells via terminals P+ / P- is prohibited
1
.
The cell charging threshold function can be switched
ON or OFF by the user, by setting bit SWCEN in the
configuration register (Table 7) using the WCFIG
command. In the case that this cell charge enable
function is switched OFF, then
V
CE
is effectively set to
0V.
Neither the X3100 nor the X3101 enter sleep mode
(automatically or manually, by setting the SLP bit) if V
CC
V
SLR
. This is to ensure that the device does not go
into a sleep mode while the battery cells are at a high
voltage (e.g. during cell charging).
Table 21. Typical Over-discharge Delay Times
Symbol
Description
Over-discharge
detection delay
Over-discharge
release time
C
UV
Delay
T
UV
0.1μF
1.0s (Typ)
T
UVR
0.1μF
7ms (Typ)
1.
In this case, charging of the battery may resume ONLY if the cell
charge enable function is switched OFF by setting bit SWCEN =
1 in the configuration register (See Above, “Configuration
Register Functionality” on page 8).
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