參數(shù)資料
型號： X3100V
英文描述： QFN,GREEN,IND TEMP,T&R(ARM)
中文描述： 電池管理
文件頁數(shù)： 21/40頁
文件大?。?/td> 249K
代理商： X3100V
X3100/X3101 – Preliminary Information
Characteristics subject to change without notice.
21 of 40
REV 1.1.8 12/10/02
www.xicor.com
of four input resistors to Op Amp OP1. The feedback
resistors remain constant. This ratio of input to feedback
resistors determines the gain. Putting external resistors
in series with the inputs reduces the gain of the amplifier.
VCS
1
and VCS
2
are read at AO with respect to a DC
bias voltage of 2.5V. Therefore, the voltage range of
VCS
12
and VCS
21
changes depending upon the
direction of current flow (i.e. battery cells are in Charge
or Discharge—Table 21).
Table 26. AO Voltage Range for VCS
12
and VCS
21
AO
Cell State
VCS
12
Charge
VCS
12
Discharge
VCS
21
Charge
VCS
21
Discharge
By calculating the difference of VCS
12
and VCS
21
the
offset voltage of the internal op-amp circuitry is
cancelled. This allows for the accurate calculation of
current flow into and out of the battery cells.
Pack current is calculated using the following formula:
VOLTAGE REGULATOR
The X3100 and X3101 are able to supply peripheral
devices with a regulated 5VDC±0.5% output at pin
RGO. The voltage regulator should be configured
externally as shown in Figure 10.
The non-inverting input of OP1 is fed with a high
precision 5VDC supply. The voltage at the output of the
voltage regulator (V
RGO
) is compared to this 5V
reference via the inverting input of OP1. The output of
OP1 in turn drives the regulator pnp transistor (Q1). The
negative feedback at the regulator output maintains the
voltage at 5VDC±0.5% (including ripple) despite
changes in load, and differences in regulator transistors.
When power is applied to pin VCC of the X3100 or
X3101, V
RGO
is regulated to 5VDC±10% for a nominal
time of T
OC
+2ms. During this time period, V
RGO
is
“tuned” to attain a final value of 5VDC±0.5% (Figure 2).
The maximum current that can flow from the voltage
regulator (I
LMT
) is controlled by the current limiting
resistor (R
LMT
) connected between RGP and VCC. When
the voltage across VCC and RGP reaches a nominal
2.5V (i.e. the threshold voltage for the FET), Q2 switches
ON, shorting VCC to the base of Q1. Since the base
voltage of Q1 is now higher than the emitter voltage, Q1
switches OFF, and hence the supply current goes to zero.
Typical values for R
LMT
and I
LMT
are shown in Table 27.
In order to protect the voltage regulator circuitry from
damage in case of a short-circuit, R
LMT
≥
10
should
always be used.
Table 27. Typical Values for R
LMT
and I
LMT
R
LMT
Voltage Regulator Current Limit (I
LMT
)
10
250mA ± 50% (Typical)
25
100mA ± 50% (Typical)
50
50mA ± 50% (Typical)
When choosing the value of R
LMT
, the drive limitations
of the PNP transistor used should also be taken into
consideration. The transistor should have a gain of at
least 100 to support an output current of 250mA.
Figure 10. Voltage Regulator Operation
4KBIT EEPROM MEMORY
The X3100 and X3101 contain a CMOS 4k-bit serial
EEPROM, internally organized as 512 x 8 bits. This
memory is accessible via the SPI port, and features the
IDLock function.
The 4kbit EEPROM array can be accessed by the SPI
port at any time, even during a protection mode, except
during sleep mode. After power is applied to VCC of the
X3100 or X3101, EEREAD and EEWRITE Instructions
AO Voltage Range
2.5V
≤
AO
≤
5.0V
0V
≤
AO
≤
2.5V
0V
≤
AO
≤
2.5V
2.5V
≤
AO
≤
5.0V
Pack Current
VCS
VCS
–
(
)
2
)
(current sense resistor)
-------- gain setting
=
VCC
RGC
RGP
RGO
Voltage
Reference
_
+
To Internal Voltage
Regulating Circuitry
Regulated
5VDC Output
R
LMT
Q1
Un-Regulated
Voltage
Input
I
LMT
Precision
X3100/X3101
OP1
5VDC
Q2
Tuning
V
RGO
0.1
μF
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