參數(shù)資料
型號(hào)： X68C75 SLIC
英文描述： Port Expander and EE Memory(端口擴(kuò)展，多重地址/數(shù)據(jù)總線，高速CMOS,微控制器外圍芯片)
中文描述： 端口擴(kuò)展和EE記憶體（端口擴(kuò)展，多重地址/數(shù)據(jù)總線，高速的CMOS微控制器外圍芯片）
文件頁數(shù)： 4/28頁
文件大小： 238K
代理商： X68C75 SLIC
4
X68C75 SLIC
E
2
determine the early completion of a write cycle. During
the internal programming cycle, I/O
6
will toggle from “1”
to “0” and “0” to “1” on subsequent attempts to read from
the memory plane that is being updated. When the
internal cycle is complete, the toggling will cease and the
device will be accessible for additional read or write
operations. Due to the dual plane architecture, reads for
polling must occur from the plane that was written; that
is, the state of A
12
during a write must match the state of
A
12
during polling.
DATA PROTECTION
The X68C75 provides two levels of data protection
through software control. There is a global software data
protection feature similar to the industry standard for
E
2
PROMs and a new Block Lock Protect write lockout
protection providing a secondary level data security
option.
Figure 1. Toggle Bit Polling E Control
CE
AS
A/D0–A/D7
A8–A12
E
R/W
AIN
DIN
A12=n
OPERATION
LAST BYTE
WRITTEN
I/O6=X
X68C75 READY FOR
NEXT OPERATION
2899 ILL F05
AIN
DOUT
A12=n
AIN
DOUT
A12=n
AIN
DOUT
A12=n
AIN
A12=n
AIN
ADDR
I/O6=X
I/O6=X
I/O6=X
DOUT
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