參數(shù)資料
型號(hào): X76F100M8
英文描述: 1K 128 x 8 Bit
中文描述: 每1000 128 × 8位
文件頁(yè)數(shù): 9/17頁(yè)
文件大?。?/td> 275K
代理商: X76F100M8
X76F100
Characteristics subject to change without notice.
9 of 16
REV 1.0 6/22/00
www.xicor.com
AC CHARACTERISTICS
(T
A
= -40
°
C to +85
°
C, V
CC
= +3.0V to +5.5V, unless otherwise specified.)
Notes:
(1) These Specs are not defined in the ISO 7816-3 Standard, since CS is not defined.
(2) C
b
= total capacitance of one bus line in pF
(3) t
AA
= 1.1μs Max below V
CC
= 3.0V.
RESET AC SPECIFICATIONS
Power Up Timing
Notes:
(1) Delays are measured from the time V
CC
s stable until the specified operation can be nitiated. These parameters are periodically sampled
and not 100% tested.
(2) Typical values are for T
A
= 25°C and V
CC
= 5.0V
Symbol
f
SCL
t
AA
(3)
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
t
DH
t
NOL
t
RDV
t
CDV
t
DHZ
(1)
t
SR
(1)
t
RST
t
SU:RST
t
SU:CS
t
SU:CS
Parameter
Min.
0
0.1
1.2
0.6
1.2
0.6
0.6
10
100
Max.
1
0.9
Unit
MHz
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
μs
μs
ns
ns
ns
ns
ns
μs
ns
ns
ns
SCL Clock Frequency
SCL LOW to SDA Data Out Valid
Time the Bus Must Be Free Before a New Transmission Can Start
Start Condition Hold Time
Clock LOW Period
Clock HIGH Period
Start Condition Setup Time (for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
RST to SCL Non-Overlap
RST LOW to SDA Valid During Response to Reset
CLK LOW to SDA Valid During Response to Reset
Device Deselect to SDA high impedance
Device Select to RST active
RST High Time
RST Setup Time
CS
Setup Time
CS
Hold Time
20+0.1XC
b
(2)
20+0.1XC
b
(2)
0.6
0
500
0
0
0
0
1.5
500
200
100
300
300
450
450
450
Symbol
t
PUR
(1)
t
PUW
(1)
Parameter
Min.
Typ.
(2)
Max.
1
5
Unit
ms
ms
Time from Power Up to Read
Time from Power Up to Write
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X76F100M8I 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:1K 128 x 8 Bit
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X76F100P 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:1K 128 x 8 Bit
X76F100P-3.0 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:1K 128 x 8 Bit