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參數(shù)資料
| 型號： | X9250UV24IZ-2.7 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC XDCP QUAD 256TP 50K 24-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Industrial Control Applications |
| 標準包裝： | 62 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 4 |
| 溫度系數(shù)： | 標準值 ±300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | 6 線 SPI（芯片選擇，設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 管件 |
5
FN8165.3
August 29, 2006
Figure 1. Detailed Potentiometer Block Diagram
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by a write in process bit
(WIP). The WIP bit is read with a read status
command.
INSTRUCTIONS
Identification (ID) Byte
The first byte sent to the X9250 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier, for the
X9250 this is fixed as 0101[B] (refer to Figure 2).
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A0 - A1 input
pins. The X9250 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9250 to successfully
continue the command sequence. The A0 - A1 inputs
can be actively driven by CMOS input signals or tied to
VCC or VSS.
The remaining two bits in the slave byte must be set to 0.
Figure 2. Identification Byte Format
Instruction Byte
The next byte sent to the X9250 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the four pots and, when applicable,
they point to one of four associated registers. The
format is shown below in Figure 3.
Figure 3. Instruction Byte Format
Serial Data Path
From Interface
Circuitry
Register 0
Register 1
Register 2
Register 3
Serial
Bus
Input
Parallel
Input
Counter
Register
Inc/Dec
Logic
UP/DN
CLK
Modified SCK
UP/DN
VH/RH
VL/RL
VW/RW
88
C
o
u
n
t
e
r
D
e
c
o
d
e
If WCR = 00[H] then VW/RW = VL/RL
If WCR = FF[H] then VW/RW = VH/RH
Wiper
(One of Four Arrays)
(WCR)
Bus
1
00
0
A1
A0
Device Type
Identifier
Device Address
1
I1
I2
I3
I0
R1
R0
P1
P0
Pot Select
Register
Select
Instructions
X9250
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X9250UV24Z-2.7 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad Digitally Controlled Potentiometers |
| X9250UZ24 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DIGITAL POTENTIOMETER|CMOS|BGA|24PIN|PLASTIC |
| X9250UZ24-2.7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DIGITAL POTENTIOMETER|CMOS|BGA|24PIN|PLASTIC |
| X9250UZ24I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DIGITAL POTENTIOMETER|CMOS|BGA|24PIN|PLASTIC |
| X9250UZ24I-2.7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DIGITAL POTENTIOMETER|CMOS|BGA|24PIN|PLASTIC |
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