FN8167.2 November 14, 2005 Test Circuit Equivalent Circuit Principles of Operation The X9252 is an integrated circuit incor" />
參數(shù)資料
型號(hào)： X9252UV24IZ-2.7
廠商： Intersil
文件頁(yè)數(shù)： 19/20頁(yè)
文件大?。?/td> 0K
描述： IC POT DGTL QUAD 50K OHM 24TSSOP
標(biāo)準(zhǔn)包裝： 62
系列： XDCP™
接片： 256
電阻（歐姆）： 50k
電路數(shù)： 4
溫度系數(shù)： 標(biāo)準(zhǔn)值 ±300 ppm/°C
存儲(chǔ)器類(lèi)型： 非易失
接口： I²C（芯片選擇，設(shè)備位址，增/減）
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 管件
8
FN8167.2
November 14, 2005
Test Circuit
Equivalent Circuit
Principles of Operation
The X9252 is an integrated circuit incorporating four resistor
arrays, their associated registers and counters, and the
serial interface logic providing direct communication
between the host and the digitally controlled potentiometers.
This section provides detail description of the following:
-Resistor Array
- Up/Down Interface
- 2-wire Interface
Resistor Array Description
The X9252 is comprised of four resistor arrays. Each array
contains 255 discrete resistive segments that are connected
in series. The physical ends of each array are equivalent to
the fixed terminals of a mechanical potentiometer (RHi and
RLi inputs) (See Figure 1.)
At both ends of each array and between each resistor
segment is a switch connected to the wiper (RWi) pin.
Within each individual array only one switch may be turned
on at a time.
These switches are controlled by a Wiper Counter Register
(WCR). The 8-bits of the WCR (WCR[7:0]) are decoded to
select and enable one of 256 switches (see Table 1). Note
that each wiper has a dedicated WCR. When all bits of a
WCR are zeroes, the switch closest to the corresponding RL
pin is selected. When all bits of a WCR are ones, the switch
closest to the corresponding RH pin is selected.
The WCR is volatile and may be written directly. There are
four non-volatile Data Registers (DR) associated with each
WCR. Each DR can be loaded into WCR. All DRs and
WCRs can be read or written.
Power Up and Down Requirements
During power up, CS must be high, to avoid inadvertant
“store” operations. At power up, the contents of Data
Registers DR00, DR10, DR20, and DR30, are loaded into
the corresponding wiper counter register.
Force
Current
Test Point
RW
CH
CL
RW
RTOTAL
CW
RH
RL
One
WCR[7:0]
RHi
RWi
RLi
= FF hex
255
254
253
252
of
256
Decoder
Volatile
8-bit
Wiper
Counter
Register
WCRi
Four
Non-Volatile
Data
Registers
DRi0, DRi1,
DRi2, and
DRi3
i = 0, 1, 2, and 3
Interface Control and
WCR[7:0]
= 00 hex
2
1
0
Volatile Status Register (SR)
(Shared by the Four DCPs)
WP
SCL
SDA
A2, A1, A0
CS
U/D
DS1, DS0
FIGURE 1. DETAILED BLOCK DIAGRAM OF ONE DCP
X9252
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