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參數(shù)資料
| 型號： | X9400YZ24 |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | Quad Digitally Controlled Potentiometers (XDCP) |
| 中文描述： | 四重數(shù)控電位器（數(shù)字電位器） |
| 文件頁數(shù)： | 4/22頁 |
| 文件大小： | 150K |
| 代理商： | X9400YZ24 |
X9400
Characteristics subject to change without notice.
4 of 22
REV 1.1.4 10/11/02
www.xicor.com
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received by
the device. The progress of this internal write operation
can be monitored by a write in process bit (WIP). The
WIP bit is read with a read status command.
INSTRUCTIONS
Identification (ID) Byte
The first byte sent to the X9400 from the host, following
a CS going HIGH to LOW, is called the Identification
byte. The most significant four bits of the slave address
are a device type identifier, for the X9400 this is fixed
as 0101[B] (refer to Figure 2).
The two least significant bits in the ID byte select one of
four devices on the bus. The physical device address is
defined by the state of the A
0
-A
1
input pins. The X9400
compares the serial data stream with the address input
state; a successful compare of both address bits is
required for the X9400 to successfully continue the
command sequence. The A
0
–A
1
inputs can be actively
driven by CMOS input signals or tied to V
CC
or V
SS
.
The remaining two bits in the slave byte must be set to 0.
Figure 2. Identification Byte Format
Instruction Byte
The next byte sent to the X9400 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the four pots and, when applicable,
they point to one of four associated registers. The
format is shown below in Figure 3.
1
0
0
0
0
A1
A0
Device Type
Identifier
Device Address
1
Figure 1. Detailed Potentiometer Block Diagram
Serial Data Path
From Interface
Circuitry
Register 0
Register 1
Register 2
Register 3
Serial
Bus
Input
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
INC/DEC
Logic
UP/DN
CLK
Modified SCL
UP/DN
V
H
/R
H
V
L
/R
L
V
W
/R
W
If WCR = 00[H] then V
W
/R
W
= V
L
/R
L
If WCR = 3F[H] then V
W
/R
W
= V
H
/R
H
8
6
C
o
u
n
t
e
r
D
e
c
o
d
e
(One of Four Arrays)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X9400YZ24I-2.7 | Quad Digitally Controlled Potentiometers (XDCP) |
| X9400 | RF/Microwave Capacitor; Capacitance:20pF; Capacitance Tolerance:+/- 5%; Series:MC; Capacitor Dielectric Material:Mica; Termination:SMD; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No RoHS Compliant: No |
| X9400WP24 | Digital Potentiometer |
| X9400WP24-2.7 | Digital Potentiometer |
| X9400WP24I | Digital Potentiometer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X9400YZ24I-2.7 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Quad Digitally Controlled Potentiometers (XDCP) |
| X9401 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Noise/Low Power/SPI Bus |
| X9401_06 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad, 64 Tap, Digitally Controlled Potentiometer |
| X9401_09 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad, 64 Tap, Digitally Controlled Potentiometer (XDCP?) |
| X94012011-01 | 功能描述:以太網(wǎng)模塊 XPress-Pro SW 94012F 8-Port 10/100TX RoHS:否 制造商:Lantronix 產(chǎn)品:Device Servers 數(shù)據(jù)速率:300 bps to 921.6 kbps, 10 Mbps, 100 Mbps 接口類型:Ethernet, Serial 工作電源電壓:5 V to 15 V 工作電源電流:133 mA to 400 mA 最大工作溫度:+ 70 C |
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