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參數(shù)資料
| 型號： | X9520 |
| 英文描述： | Triple DCP, POR, 2 kbit EEPROM Memory, Dual Voltage Monitors(3個(gè)DCP,上電復(fù)位,2k位串行EEPROM,分別的雙電壓監(jiān)控器端電壓-1.0~+15V) |
| 中文描述： | 三氯酚，葡萄牙，2千比特EEPROM存儲器，雙電壓監(jiān)視器（3個(gè)副處長，上電復(fù)位和2K位串行EEPROM中，分別的雙電壓監(jiān)控器端電壓-1.0?15V的） |
| 文件頁數(shù)： | 3/34頁 |
| 文件大小： | 210K |
| 代理商： | X9520 |
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REV 1.3 4/13/04
Characteristics subject to change without notice.
3 of 34
www.xicor.com
X9520
– Preliminary Information
PIN ASSIGNMENT
TSSOP
CSP
Name
Function
1
B3
R
H2
Connection to end of resistor array for (the 256 Tap) DCP 2.
2
A3
R
w2
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.
3
A4
R
L2
Connection to other end of resistor array for (the 256 Tap) DCP2.
4
B4
V3
V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit.
When the V3 input is higher than the
V
TRIP3
to a HIGH level. Connect V3 to V
SS
when not used.
V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is
greater than
V
TRIP3
and goes LOW when V3 is less than VTRIP3. There is no delay cir-
cuitry on this pin. The V3RO pin requires the use of an external “pull-up” resistor.
threshold voltage, V3RO makes a transition
5
C3
V3RO
6
D3
MR
Manual Reset. MR is a TTL level compatible input. Pulling the MR pin active (HIGH) ini-
tiates a reset cycle to the V1RO pin (V1 / Vcc RESET Output pin). V1RO will remain HIGH
for time t
purst
after MR has returned to it’s normally LOW state. The reset time can be se-
lected using bits POR1 and POR0 in the CONSTAT Register. The MR pin requires the use
of an external “pull-down” resistor.
7
C4
WP
Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write
Protection is enabled. In the enabled state, this pin prevents all nonvolatile “write” opera-
tions. Also, when the Write Protection is enabled, and the device Block Lock feature is active
(i.e. the Block Lock bits are NOT [0,0]), then no “write” (volatile or nonvolatile) operations
can be performed in the device (including the wiper position of any of the integrated Digitally
Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-down” resistor, thus if
left floating the write protection feature is disabled.
8
D4
SCL
Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing
for data input and output.
9
E4
SDA
Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and
out of the device. The SDA pin input buffer is always active (not gated). This pin requires
an external pull up resistor.
10
E1
Vss
Ground.
11
E3
R
L1
Connection to other end of resistor for (the 100 Tap) DCP 1.
12
E2
R
w1
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1
13
D1
R
H1
Connection to end of resistor array for (the 100 Tap) DCP 1.
14
D2
R
H0
Connection to end of resistor array for (the 64 Tap) Digitally Controlled Potentiometer
(DCP) 0.
15
C1
R
W0
R
L0
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 0.
16
C2
Connection to the other end of resistor array for (the 64 Tap) DCP 0.
17
B1
V2
V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit.
When the V2 input is greater than the
V
TRIP2
threshold voltage, V2RO makes a transition
to a HIGH level. Connect V2 to V
SS
when not used.
V2 RESET Output. This open drain output makes a transition to a HIGH level when V2 is
greater than
V
TRIP2
, and goes LOW when V2 is less than
reset delay circuitry on this pin. The V2RO pin requires the use of an external “pull-up” re-
sistor.
18
A1
V2RO
V
TRIP2
. There is no power up
19
B2
V1RO
V1 / Vcc RESET Output. This is an active HIGH, open drain output which becomes active
whenever V1 / Vcc falls below
V
TRIP1
. V1RO becomes active on power up and remains
active for a time t
purst
after the power supply stabilizes (t
the POR0 and POR1 bits of the internal control register). The V1RO pin requires the use
of an external “pull-up” resistor. The V1RO pin can be forced active (HIGH) using the man-
ual reset (MR) input pin.
purst
can be changed by varying
20
A2
V1 / Vcc
Supply Voltage.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X9520_06 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple DCP, POR, 2kbit EEPROM Memory, Dual Voltage Monitors |
| X9520_07 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple DCP, POR, 2kbit EEPROM Memory, Dual Voltage Monitors |
| X9520B20IA | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple DCP, POR,2kbit EEPROM Memory, Dual Voltage Monitors |
| X9520B20I-A | 功能描述:IC LASR CTRLR 3CHAN 5.5V 20TSSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 激光驅(qū)動器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:60 系列:- 類型:激光二極管驅(qū)動器 數(shù)據(jù)速率:- 通道數(shù):4 電源電壓:3.3V 電流 - 電源:- 電流 - 調(diào)制:- 電流 - 偏置:- 工作溫度:0°C ~ 70°C 封裝/外殼:40-TQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN EP 包裝:托盤 安裝類型:表面貼裝 |
| X9520B20I-AT1 | 功能描述:IC LASR CTRLR 3CHAN 5.5V 20TSSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 激光驅(qū)動器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:60 系列:- 類型:激光二極管驅(qū)動器 數(shù)據(jù)速率:- 通道數(shù):4 電源電壓:3.3V 電流 - 電源:- 電流 - 調(diào)制:- 電流 - 偏置:- 工作溫度:0°C ~ 70°C 封裝/外殼:40-TQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN EP 包裝:托盤 安裝類型:表面貼裝 |
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