參數資料
型號: XA3S500E-4FTG256Q
廠商: Xilinx Inc
文件頁數: 18/37頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN-3E 500K 256FTBGA
標準包裝: 90
系列: Spartan®-3E XA
LAB/CLB數: 1164
邏輯元件/單元數: 10476
RAM 位總計: 368640
輸入/輸出數: 190
門數: 500000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 125°C
封裝/外殼: 256-LBGA
供應商設備封裝: 256-FTBGA
DS635 (v2.0) September 9, 2009
Product Specification
25
R
Delay-Locked Loop
Table 26: Recommended Operating Conditions for the DLL
Symbol
Description
-4 Speed Grade
Units
Min
Max
Input Frequency Ranges
FCLKIN
CLKIN_FREQ_DLL
Frequency of the CLKIN clock input
5(2)
240(3)
MHz
Input Pulse Requirements
CLKIN_PULSE
CLKIN pulse width as a
percentage of the CLKIN
period
FCLKIN < 150 MHz
40%
60%
-
FCLKIN > 150 MHz
45%
55%
-
Input Clock Jitter Tolerance and Delay Path Variation(4)
CLKIN_CYC_JITT_DLL_LF
Cycle-to-cycle jitter at the
CLKIN input
FCLKIN < 150 MHz
-±300
ps
CLKIN_CYC_JITT_DLL_HF
FCLKIN > 150 MHz
-±150
ps
CLKIN_PER_JITT_DLL
Period jitter at the CLKIN input
-±1
ns
CLKFB_DELAY_VAR_EXT
Allowable variation of off-chip feedback delay from the DCM output to
the CLKFB input
-±1
ns
Notes:
1.
DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
2.
The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table 28.
3.
To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock frequency by two as it enters the DCM. The CLK2X output reproduces the clock frequency provided on the CLKIN input.
4.
CLKIN input jitter beyond these limits might cause the DCM to lose lock.
Table 27: Switching Characteristics for the DLL
Symbol
Description
-4 Speed Grade
Units
Min
Max
Output Frequency Ranges
CLKOUT_FREQ_CLK0
Frequency for the CLK0 and CLK180 outputs
5
240
MHz
CLKOUT_FREQ_CLK90
Frequency for the CLK90 and CLK270 outputs
5
200
MHz
CLKOUT_FREQ_2X
Frequency for the CLK2X and CLK2X180 outputs
10
311
MHz
CLKOUT_FREQ_DV
Frequency for the CLKDV output
0.3125
160
MHz
Output Clock Jitter(2,3,4)
CLKOUT_PER_JITT_0
Period jitter at the CLK0 output
-
±100
ps
CLKOUT_PER_JITT_90
Period jitter at the CLK90 output
-
±150
ps
CLKOUT_PER_JITT_180
Period jitter at the CLK180 output
-
±150
ps
CLKOUT_PER_JITT_270
Period jitter at the CLK270 output
-
±150
ps
CLKOUT_PER_JITT_2X
Period jitter at the CLK2X and CLK2X180 outputs
-±[1% of
CLKIN period
+ 150]
ps
CLKOUT_PER_JITT_DV1
Period jitter at the CLKDV output when performing integer
division
-
±150
ps
CLKOUT_PER_JITT_DV2
Period jitter at the CLKDV output when performing
non-integer division
-±[1% of
CLKIN period
+ 200]
ps
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