參數(shù)資料
型號(hào)： XC2S100-5FGG256C
廠商： Xilinx Inc
文件頁數(shù)： 67/99頁
文件大小： 0K
描述： IC SPARTAN-II FPGA 100K 256-FBGA
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-II
LAB/CLB數(shù)： 600
邏輯元件/單元數(shù)： 2700
RAM 位總計(jì)： 40960
輸入/輸出數(shù)： 176
門數(shù)： 100000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-FBGA（17x17）
其它名稱： 122-1302
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
7
2000-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
Architectural Description
Spartan-II FPGA Array
The Spartan-II field-programmable gate array, shown in
Figure 2, is composed of five major configurable elements:
IOBs provide the interface between the package pins
and the internal logic
CLBs provide the functional elements for constructing
most logic
Dedicated block RAM memories of 4096 bits each
Clock DLLs for clock-distribution delay compensation
and clock domain control
Versatile multi-level interconnect structure
As can be seen in Figure 2, the CLBs form the central logic
structure with easy access to all support and routing
structures. The IOBs are located around all the logic and
memory elements for easy and quick routing of signals on
and off the chip.
Values stored in static memory cells control all the
configurable logic elements and interconnect resources.
These values load into the memory cells on power-up, and
can reload if necessary to change the function of the device.
Each of these elements will be discussed in detail in the
following sections.
Input/Output Block
The Spartan-II FPGA IOB, as seen in Figure 2, features
inputs and outputs that support a wide variety of I/O
signaling standards. These high-speed inputs and outputs
are capable of supporting various state of the art memory
and bus interfaces. Table 3 lists several of the standards
which are supported along with the required reference,
output and termination voltages needed to meet the
standard.
50
Spartan-II FPGA Family:
Functional Description
DS001-2 (v2.8) June 13, 2008
Product Specification
R
Figure 2: Spartan-II FPGA Input/Output Block (IOB)
Package Pin
Package
Pin
Package Pin
D
CK
EC
SR
Q
D
CK
EC
SR
Q
D
CK
EC
SR
Q
Programmable
Bias &
ESD Network
VCCO
I/O
I/O, VREF
Internal
Reference
To Next I/O
To Other
External VREF Inputs
of Bank
Programmable
Input Buffer
Programmable
Output Buffer
Programmable
Delay
VCC
OE
SR
O
OCE
I
ICE
IQ
CLK
TCE
T
DS001_02_090600
TFF
OFF
IFF
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