參數(shù)資料
型號(hào)： XC2S15-5VQG100C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 5/99頁(yè)
文件大?。?/td> 0K
描述： IC SPARTAN-II FPGA 15K 100-VQFP
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-II
LAB/CLB數(shù)： 96
邏輯元件/單元數(shù)： 432
RAM 位總計(jì)： 16384
輸入/輸出數(shù)： 60
門(mén)數(shù)： 15000
電源電壓： 2.375 V ~ 2.625 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-VQFP（14x14）
產(chǎn)品目錄頁(yè)面： 599 (CN2011-ZH PDF)
其它名稱(chēng)： 122-1309
Spartan-II FPGA Family: Functional Description
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
13
R
Clock Distribution
The Spartan-II family provides high-speed, low-skew clock
distribution through the primary global routing resources
described above. A typical clock distribution net is shown in
Four global buffers are provided, two at the top center of the
device and two at the bottom center. These drive the four
primary global nets that in turn drive any clock pin.
Four dedicated clock pads are provided, one adjacent to
each of the global buffers. The input to the global buffer is
selected either from these pads or from signals in the
general purpose routing. Global clock pins do not have the
option for internal, weak pull-up resistors.
Delay-Locked Loop (DLL)
Associated with each global clock input buffer is a fully
digital Delay-Locked Loop (DLL) that can eliminate skew
between the clock input pad and internal clock-input pins
throughout the device. Each DLL can drive two global clock
networks. The DLL monitors the input clock and the
distributed clock, and automatically adjusts a clock delay
element. Additional delay is introduced such that clock
edges reach internal flip-flops exactly one clock period after
they arrive at the input. This closed-loop system effectively
eliminates clock-distribution delay by ensuring that clock
edges arrive at internal flip-flops in synchronism with clock
edges arriving at the input.
In addition to eliminating clock-distribution delay, the DLL
provides advanced control of multiple clock domains. The
DLL provides four quadrature phases of the source clock,
can double the clock, or divide the clock by 1.5, 2, 2.5, 3, 4,
5, 8, or 16. It has six outputs.
The DLL also operates as a clock mirror. By driving the
output from a DLL off-chip and then back on again, the DLL
can be used to deskew a board level clock among multiple
Spartan-II devices.
In order to guarantee that the system clock is operating
correctly prior to the FPGA starting up after configuration,
the DLL can delay the completion of the configuration
process until after it has achieved lock.
Boundary Scan
Spartan-II devices support all the mandatory boundary-
scan instructions specified in the IEEE standard 1149.1. A
Test Access Port (TAP) and registers are provided that
implement the EXTEST, SAMPLE/PRELOAD, and BYPASS
instructions. The TAP also supports two USERCODE
instructions and internal scan chains.
The TAP uses dedicated package pins that always operate
using LVTTL. For TDO to operate using LVTTL, the VCCO
for Bank 2 must be 3.3V. Otherwise, TDO switches
rail-to-rail between ground and VCCO. TDI, TMS, and TCK
have a default internal weak pull-up resistor, and TDO has
no default resistor. Bitstream options allow setting any of
the four TAP pins to have an internal pull-up, pull-down, or
neither.
Figure 7: BUFT Connections to Dedicated Horizontal Bus Lines
CLB
3-State
Lines
DS001_07_090600
Figure 8: Global Clock Distribution Network
Global Clock
Spine
Global Clock
Column
GCLKPAD2
GCLKBUF2
GCLKPAD3
GCLKBUF3
GCLKBUF1
GCLKPAD1
GCLKBUF0
GCLKPAD0
Global
Clock Rows
DS001_08_060100
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC2S15-5VQG100I 制造商:Xilinx 功能描述:FPGA SPARTAN-II 15K GATES 432 CELLS 263MHZ 2.5V 100VTQFP - Trays 制造商:Xilinx 功能描述:IC SYSTEM GATE
XC2S15-6CS144C 功能描述:IC FPGA 2.5V C-TEMP 144-CSBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Spartan®-II 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
XC2S15-6CS144I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-II FPGA Family
XC2S15-6CSG144C 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-II FPGA Family
XC2S15-6CSG144I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-II FPGA Family
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