參數(shù)資料
型號(hào): XC2S150-6FG256C
廠商: Xilinx Inc
文件頁(yè)數(shù): 55/99頁(yè)
文件大小: 0K
描述: IC FPGA 2.5V C-TEMP 256-FBGA
標(biāo)準(zhǔn)包裝: 90
系列: Spartan®-II
LAB/CLB數(shù): 864
邏輯元件/單元數(shù): 3888
RAM 位總計(jì): 49152
輸入/輸出數(shù): 176
門(mén)數(shù): 150000
電源電壓: 2.375 V ~ 2.625 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-FBGA(17x17)
Spartan-II FPGA Family: DC and Switching Characteristics
DS001-3 (v2.8) June 13, 2008
Module 3 of 4
Product Specification
59
R
IOB Output Delay Adjustments for Different Standards(1)
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown. A delay adjusted in this way constitutes a worst-case limit.
Symbol
Description
Standard
Speed Grade
Units
-6
-5
Output Delay Adjustments (Adj)
TOLVTTL_S2
Standard-specific adjustments for
output delays terminating at pads
(based on standard capacitive
load, CSL)
LVTTL, Slow, 2 mA
14.2
16.9
ns
TOLVTTL_S4
4 mA
7.2
8.6
ns
TOLVTTL_S6
6 mA
4.7
5.5
ns
TOLVTTL_S8
8 mA
2.9
3.5
ns
TOLVTTL_S12
12 mA
1.9
2.2
ns
TOLVTTL_S16
16 mA
1.7
2.0
ns
TOLVTTL_S24
24 mA
1.3
1.5
ns
TOLVTTL_F2
LVTTL, Fast, 2 mA
12.6
15.0
ns
TOLVTTL_F4
4 mA
5.1
6.1
ns
TOLVTTL_F6
6 mA
3.0
3.6
ns
TOLVTTL_F8
8 mA
1.0
1.2
ns
TOLVTTL_F12
12 mA
0
ns
TOLVTTL_F16
16 mA
–0.1
ns
TOLVTTL_F24
24 mA
–0.1
–0.2
ns
TOLVCMOS2
LVCMOS2
0.2
ns
TOPCI33_3
PCI, 33 MHz, 3.3V
2.4
2.9
ns
TOPCI33_5
PCI, 33 MHz, 5.0V
2.9
3.5
ns
TOPCI66_3
PCI, 66 MHz, 3.3V
–0.3
–0.4
ns
TOGTL
GTL
0.6
0.7
ns
TOGTLP
GTL+
0.9
1.1
ns
TOHSTL_I
HSTL I
–0.4
–0.5
ns
TOHSTL_III
HSTL III
–0.8
–1.0
ns
TOHSTL_IV
HSTL IV
–0.9
–1.1
ns
TOSSTL2_I
SSTL2 I
–0.4
–0.5
ns
TOSSLT2_II
SSTL2 II
–0.8
–1.0
ns
TOSSTL3_I
SSTL3 I
–0.4
–0.5
ns
TOSSTL3_II
SSTL3 II
–0.9
–1.1
ns
TOCTT
CTT
–0.5
–0.6
ns
TOAGP
AGP
–0.8
–1.0
ns
Notes:
1.
Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. For other I/O standards and different loads, see the
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