參數(shù)資料
型號: XC2S200-5FG456I
廠商: Xilinx Inc
文件頁數(shù): 41/99頁
文件大?。?/td> 0K
描述: IC FPGA 2.5V I-TEMP 456-FBGA
標(biāo)準(zhǔn)包裝: 60
系列: Spartan®-II
LAB/CLB數(shù): 1176
邏輯元件/單元數(shù): 5292
RAM 位總計(jì): 57344
輸入/輸出數(shù): 284
門數(shù): 200000
電源電壓: 2.375 V ~ 2.625 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 456-BBGA
供應(yīng)商設(shè)備封裝: 456-FBGA
Spartan-II FPGA Family: Functional Description
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
46
R
SSTL3 Class I
A sample circuit illustrating a valid termination technique for
SSTL3_I appears in Figure 47. DC voltage specifications
appear in Table 25 for the SSTL3_I standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics.
SSTL3 Class II
A sample circuit illustrating a valid termination technique for
SSTL3_II appears in Figure 48. DC voltage specifications
appear in Table 26 for the SSTL3_II standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics.
Figure 47: Terminated SSTL3 Class I
Table 25: SSTL3_I Voltage Specifications
Parameter
Min
Typ
Max
VCCO
3.0
3.3
3.6
VREF = 0.45 × VCCO
1.3
1.5
1.7
VTT = VREF
1.3
1.5
1.7
VIH ≥ VREF + 0.2
1.5
1.7
3.9(1)
VIL ≤ VREF – 0.2
–0.3(2)
1.3
1.5
VOH ≥ VREF + 0.6
1.9
-
VOL ≤ VREF – 0.6
-
1.1
IOH at VOH (mA)
–8
-
IOL at VOL (mA)
8
-
Notes:
1.
VIH maximum is VCCO + 0.3.
2.
VIL minimum does not conform to the formula.
VREF = 1.5V
VCCO = 3.3V
50
Ω
Z = 50
SSTL3 Class I
DS001_47_061200
VTT = 1.5V
25
Ω
Figure 48: Terminated SSTL3 Class II
Table 26: SSTL3_II Voltage Specifications
Parameter
Min
Typ
Max
VCCO
3.0
3.3
3.6
VREF = 0.45 × VCCO
1.3
1.5
1.7
VTT = VREF
1.3
1.5
1.7
VIH ≥ VREF + 0.2
1.5
1.7
3.9(1)
VIL ≤ VREF – 0.2
–0.3(2)
1.3
1.5
VOH ≥ VREF + 0.8
2.1
-
VOL ≤ VREF – 0.8
-
0.9
IOH at VOH (mA)
–16
-
IOL at VOL (mA)
16
-
Notes:
1.
VIH maximum is VCCO + 0.3
2.
VIL minimum does not conform to the formula
VREF = 1.5V
VCCO = 3.3V
50
Ω
Z = 50
SSTL3 Class II
DS001_48_061200
VTT = 1.5V
50
Ω
VTT = 1.5V
25
Ω
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