參數(shù)資料
型號(hào): XC2S200-6FG456C
廠商: Xilinx Inc
文件頁(yè)數(shù): 52/99頁(yè)
文件大?。?/td> 0K
描述: IC FPGA 2.5V C-TEMP 456-FBGA
標(biāo)準(zhǔn)包裝: 60
系列: Spartan®-II
LAB/CLB數(shù): 1176
邏輯元件/單元數(shù): 5292
RAM 位總計(jì): 57344
輸入/輸出數(shù): 284
門數(shù): 200000
電源電壓: 2.375 V ~ 2.625 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 456-BBGA
供應(yīng)商設(shè)備封裝: 456-FBGA
Spartan-II FPGA Family: DC and Switching Characteristics
DS001-3 (v2.8) June 13, 2008
Module 3 of 4
Product Specification
56
R
IOB Input Switching Characteristics(1)
Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values
Symbol
Description
Device
Speed Grade
Units
-6
-5
Min
Max
Min
Max
Propagation Delays
TIOPI
Pad to I output, no delay
All
-
0.8
-
1.0
ns
TIOPID
Pad to I output, with delay
All
-
1.5
-
1.8
ns
TIOPLI
Pad to output IQ via transparent latch,
no delay
All
-
1.7
-
2.0
ns
TIOPLID
Pad to output IQ via transparent latch,
with delay
XC2S15
-
3.8
-
4.5
ns
XC2S30
-
3.8
-
4.5
ns
XC2S50
-
3.8
-
4.5
ns
XC2S100
-
3.8
-
4.5
ns
XC2S150
-
4.0
-
4.7
ns
XC2S200
-
4.0
-
4.7
ns
Sequential Delays
TIOCKIQ
Clock CLK to output IQ
All
-
0.7
-
0.8
ns
Setup/Hold Times with Respect to Clock CLK(2)
TIOPICK / TIOICKP
Pad, no delay
All
1.7 / 0
-
1.9 / 0
-
ns
TIOPICKD / TIOICKPD Pad, with delay(1)
XC2S15
3.8 / 0
-
4.4 / 0
-
ns
XC2S30
3.8 / 0
-
4.4 / 0
-
ns
XC2S50
3.8 / 0
-
4.4 / 0
-
ns
XC2S100
3.8 / 0
-
4.4 / 0
-
ns
XC2S150
3.9 / 0
-
4.6 / 0
-
ns
XC2S200
3.9 / 0
-
4.6 / 0
-
ns
TIOICECK / TIOCKICE ICE input
All
0.9 / 0.01
-
0.9 / 0.01
-
ns
Set/Reset Delays
TIOSRCKI
SR input (IFF, synchronous)
All
-
1.1
-
1.2
ns
TIOSRIQ
SR input to IQ (asynchronous)
All
-
1.5
-
1.7
ns
TGSRQ
GSR to output IQ
All
-
9.9
-
11.7
ns
Notes:
1.
Input timing for LVTTL is measured at 1.4V. For other I/O standards, see the table "Delay Measurement Methodology," page 60.
2.
A zero hold time listing indicates no hold time or a negative hold time.
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