Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics
16
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DS077-3 (v2.0) November 18, 2002
Product Specification
R
CLB Arithmetic Switching Characteristics
Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment
listed. Precise values are provided by the timing analyzer.
Symbol
Description
Speed Grade
Units
-7
-6
Min
Max
Min
Max
Combinatorial Delays
T
OPX
T
OPXB
T
OPY
T
OPYB
T
OPCYF
T
OPGY
T
OPGYB
T
OPCYG
T
BXCY
T
CINX
T
CINXB
T
CINY
T
CINYB
T
BYP
F operand inputs to X via XOR
-
0.8
-
0.8
ns
F operand input to XB output
-
0.8
-
0.9
ns
F operand input to Y via XOR
-
1.4
-
1.5
ns
F operand input to YB output
-
1.1
-
1.3
ns
F operand input to COUT output
-
0.9
-
1.0
ns
G operand inputs to Y via XOR
-
0.8
-
0.9
ns
G operand input to YB output
-
1.2
-
1.3
ns
G operand input to COUT output
-
0.9
-
1.0
ns
BX initialization input to COUT
-
0.51
-
0.6
ns
CIN input to X output via XOR
-
0.6
-
0.7
ns
CIN input to XB
-
0.07
-
0.1
ns
CIN input to Y via XOR
-
0.7
-
0.7
ns
CIN input to YB
-
0.4
-
0.5
ns
CIN input to COUT output
-
0.14
-
0.15
ns
Multiplier Operation
T
FANDXB
T
FANDYB
T
FANDCY
T
GANDYB
T
GANDCY
Setup/Hold Times with Respect to Clock CLK
F1/2 operand inputs to XB output via AND
-
0.35
-
0.4
ns
F1/2 operand inputs to YB output via AND
-
0.7
-
0.8
ns
F1/2 operand inputs to COUT output via AND
-
0.5
-
0.6
ns
G1/2 operand inputs to YB output via AND
-
0.6
-
0.7
ns
G1/2 operand inputs to COUT output via AND
-
0.3
-
0.4
ns
T
CCKX
/ T
CKCX
T
CCKY
/ T
CKCY
CIN input to FFX
1.2 / 0
-
1.3 / 0
-
ns
CIN input to FFY
1.2 / 0
-
1.3 / 0
-
ns