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參數(shù)資料
| 型號： | XC3064L-8TQ144I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 47/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 3.3V I-TEMP 144-TQFP |
| 產(chǎn)品變化通告： | XC3000(L) Discontinuation 01/Feb/2003 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | XC3000A/L |
| LAB/CLB數(shù)： | 224 |
| RAM 位總計： | 46064 |
| 輸入/輸出數(shù)： | 120 |
| 門數(shù)： | 4500 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
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R
November 9, 1998 (Version 3.1)
7-53
XC3000 Series Field Programmable Gate Arrays
7
XC3100A Switching Characteristics
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released
device performance parameters, please request a copy of the current test-specification revision.
XC3100A Operating Conditions
Note:
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per
°C.
XC3100A DC Characteristics Over Operating Conditions
Notes: 1. With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND, and the LCA
device configured with a tie option.
2. Total continuous output sink current may not exceed 100 mA per ground pin. The number of ground pins varies from two for
the XC3120A in the PC84 package, to eight for the XC3195A in the PQ208 package.
3. Not tested. Allows an undriven pin to float High. For any other purpose, use an external pull-up.
Symbol
Description
Min
Max
Units
VCC
Supply voltage relative to GND Commercial 0
°C to +85°C junction
4.25
5.25
V
Supply voltage relative to GND Industrial -40
°C to +100°C junction
4.5
5.5
V
VIHT
High-level input voltage — TTL configuration
2.0
VCC
V
VILT
Low-level input voltage — TTL configuration
0
0.8
V
VIHC
High-level input voltage — CMOS configuration
70%
100%
VCC
VILC
Low-level input voltage — CMOS configuration
0
20%
VCC
TIN
Input signal transition time
250
ns
Symbol
Description
Min
Max
Units
VOH
High-level output voltage (@ IOH = –8.0 mA, VCC min)
Commercial
3.86
V
VOL
Low-level output voltage (@ IOL = 8.0 mA, VCC min)
0.40
V
VOH
High-level output voltage (@ IOH = –8.0 mA, VCC min)
Industrial
3.76
V
VOL
Low-level output voltage (@ IOL = 8.0 mA, VCC min)
0.40
V
VCCPD
Power-down supply voltage (PWRDWN must be Low)
2.30
V
ICCO
Quiescent LCA supply current in addition to ICCPD
1
Chip thresholds programmed as CMOS levels
Chip thresholds programmed as TTL levels
8
14
mA
IIL
Input Leakage Current
–10
+10
A
CIN
Input capacitance, all packages except PGA175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
10
15
pF
Input capacitance, PGA 175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
15
20
pF
IRIN
Pad pull-up (when selected) @ VIN = 0 V
3
0.02
0.17
mA
IRLL
Horizontal Longline pull-up (when selected) @ logic Low
0.20
2.80
mA
Product Obsolete or Under Obsolescence
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