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參數(shù)資料
| 型號： | XC3064L-8TQ144I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 7/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 3.3V I-TEMP 144-TQFP |
| 產(chǎn)品變化通告： | XC3000(L) Discontinuation 01/Feb/2003 |
| 標準包裝： | 60 |
| 系列： | XC3000A/L |
| LAB/CLB數(shù)： | 224 |
| RAM 位總計： | 46064 |
| 輸入/輸出數(shù)： | 120 |
| 門數(shù)： | 4500 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 144-LQFP |
| 供應商設備封裝： | 144-TQFP（20x20） |
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R
November 9, 1998 (Version 3.1)
7-17
XC3000 Series Field Programmable Gate Arrays
7
A buffer in the upper left corner of the FPGA chip drives a
global net which is available to all K inputs of logic blocks.
Using the global buffer for a clock signal provides a
skew-free, high fan-out, synchronized clock for use at any
or all of the IOBs and CLBs. Configuration bits for the K
input to each logic block can select this global line or
another routing resource as the clock source for its
flip-flops. This net may also be programmed to drive the die
edge clock lines for IOB use. An enhanced speed, CMOS
threshold, direct access to this buffer is available at the sec-
ond pad from the top of the left die edge.
A buffer in the lower right corner of the array drives a hori-
zontal Longline that can drive programmed connections to
a vertical Longline in each interconnection column. This
alternate buffer also has low skew and high fan-out. The
network formed by this alternate buffer’s Longlines can be
selected to drive the K inputs of the CLBs. CMOS thresh-
old, high speed access to this buffer is available from the
third pad from the bottom of the right die edge.
Internal Busses
A pair of 3-state buffers, located adjacent to each CLB, per-
mits logic to drive the horizontal Longlines. Logic operation
of the 3-state buffer controls allows them to implement wide
multiplexing functions. Any 3-state buffer input can be
selected as drive for the horizontal long-line bus by apply-
ing a Low logic level on its 3-state control line. See
Figure 16. The user is required to avoid contention which
can result from multiple drivers with opposing logic levels.
Control of the 3-state input by the same signal that drives
the buffer input, creates an open-drain wired-AND function.
A logic High on both buffer inputs creates a high imped-
ance, which represents no contention. A logic Low enables
the buffer to drive the Longline Low. See Figure 17. Pull-up
resistors are available at each end of the Longline to pro-
vide a High output when all connected buffers are non-con-
ducting. This forms fast, wide gating functions. When data
drives the inputs, and separate signals drive the 3-state
control lines, these buffers form multiplexers (3-state bus-
ses). In this case, care must be used to prevent contention
through multiple active buffers of conflicting levels on a
common line. Each horizontal Longline is also driven by a
weak keeper circuit that prevents undefined floating levels
by maintaining the previous logic level when the line is not
driven by an active buffer or a pull-up resistor. Figure 18
shows 3-state buffers, Longlines and pull-up resistors.
3-STATE CONTROL
GG
HG
P40
P41
P42
P43
RST
P46
.l
X1245
.q
.Q
OS
C
P47
BCL
KIN
P48
GH
HH
.lk
.ck
I/O CLOCKS
BIDIRECTIONAL
INTERCONNECT
BUFFERS
GLOBAL NET
3 VERTICAL LONG
LINES PER COLUMN
HORIZONTAL LONG LINE
PULL-UP RESISTOR
HORIZONTAL LONG LINE
OSCILLATOR
AMPLIFIER OUTPUT
DIRECTINPUT OF P47
TO AUXILIARY BUFFER
CRYSTAL OSCILLATOR
BUFFER
3-STATE INPUT
3-STATE BUFFER
ALTERNATE BUFFER
D
P
G
M
Figure 18: Design Editor.
An extra large view of possible interconnections in the lower right corner of the XC3020A.
Product Obsolete or Under Obsolescence
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