參數(shù)資料
型號(hào)： XC3090L-8PC84I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 23/76頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 3.3V I-TEMP 84-PLCC
產(chǎn)品變化通告： XC3000(L) Discontinuation 01/Feb/2003
標(biāo)準(zhǔn)包裝： 15
系列： XC3000A/L
LAB/CLB數(shù)： 320
RAM 位總計(jì)： 64160
輸入/輸出數(shù)： 70
門(mén)數(shù)： 6000
電源電壓： 3 V ~ 3.6 V
安裝類(lèi)型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 84-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 84-PLCC
R
November 9, 1998 (Version 3.1)
7-5
XC3000 Series Field Programmable Gate Arrays
7
Improvements in the XC3000A and XC3000L
Families
The XC3000A and XC3000L families offer the following
enhancements over the popular XC3000 family:
The XC3000A and XC3000L families have additional inter-
connect resources to drive the I-inputs of TBUFs driving
horizontal Longlines. The CLB Clock Enable input can be
driven from a second vertical Longline. These two additions
result in more efficient and faster designs when horizontal
Longlines are used for data bussing.
During configuration, the XC3000A and XC3000L devices
check the bit-stream format for stop bits in the appropriate
positions. Any error terminates the configuration and pulls
INIT Low.
When the configuration process is finished and the device
starts up in user mode, the first activation of the outputs is
automatically slew-rate limited. This feature, called Soft
Startup, avoids the potential ground bounce when all
out-puts are turned on simultaneously. After start-up, the
slew rate of the individual outputs is, as in the XC3000 fam-
ily, determined by the individual configuration option.
Improvements in the XC3100A and XC3100L
Families
Based on a more advanced CMOS process, the XC3100A
and XC3100L families are architecturally-identical, perfor-
mance-optimized relatives of the XC3000A and XC3000L
families. While all families are footprint compatible, the
XC3100A family extends achievable system performance
beyond 85 MHz.
XC3100
XC3100A
(XC3195A)
Gate
Capacity
X7068
Functionality
XC3000L
XC3000A
XC3100L
Speed
Figure 1: XC3000 FPGA Families
Product Obsolete or Under Obsolescence
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