參數(shù)資料
型號： XC3090L-8PC84I
廠商： Xilinx Inc
文件頁數(shù)： 32/76頁
文件大小： 0K
描述： IC FPGA 3.3V I-TEMP 84-PLCC
產(chǎn)品變化通告： XC3000(L) Discontinuation 01/Feb/2003
標(biāo)準(zhǔn)包裝： 15
系列： XC3000A/L
LAB/CLB數(shù)： 320
RAM 位總計： 64160
輸入/輸出數(shù)： 70
門數(shù)： 6000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 84-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 84-PLCC
R
XC3000 Series Field Programmable Gate Arrays
7-40
November 9, 1998 (Version 3.1)
Pin Functions During Configuration
Configuration Mode <M2:M1:M0>
***
**
****
SLAVE
SERIAL
<1:1:1>
MASTER-
SERIAL
<0:0:0>
PERIPH
<1:0:1>
MASTER-
HIGH
<1:1:0>
MASTER-
LOW
<1:0:0>
44
PLCC
64
VQFP
68
PLCC
84
PLCC
84
PGA
100
PQFP
100
VQFP
TQFP
132
PGA
144
TQFP
160
PQFP
175
PGA
176
TQFP
208
PQFP
User
Function
POWR
DWN
(I)
POWER
DWN
(I)
POWER
DWN
(I)
POWER
DWN
(I)
POWER
DWN
(I)
7
17
10
12
B2
29
26
A1
1
159
B2
1
3
POWER
DWN
(1)
M1 (HIGH) (I)
M1 (LOW) (I)
M1 (HIGH) (I)
M1 (LOW) (I)
16
31
25
31
J2
52
49
B13
36
40
B14
45
48
RDATA
M0 (HIGH) (I)
M0 (LOW) (I)
M0 (HIGH) (I)
M0 (LOW) (I)
17
32
26
32
L1
54
51
A14
38
42
B15
47
50
RTRIG (I)
M2 (HIGH) (I)
M2 (LOW) (I)
M2 (HIGH) (I)
18
33
27
33
K2
56
53
C13
40
44
C15
49
56
I/O
HDC (HIGH)
19
34
28
34
K3
57
54
B14
41
45
E14
50
57
I/O
LDC (LOW)
20
36
30
36
L3
59
56
D14
45
49
D16
54
61
I/O
INIT*
2240
34
42
K6
6562
G14
5359
H15
6577
I/O
GND
23
41
35
43
J6
66
63
H12
55
61
J14
67
79
GND
26
47
43
53
L11
76
73
M13
69
76
P15
85
100
XTL2 OR I/O
RESET (I)
27
48
44
54
K10
78
75
P14
71
78
R15
87
102
RESET (I)
DONE
28
49
45
55
J10
80
77
N13
73
80
R14
89
107
PROGRAM (I)
DATA 7 (I)
50
46
56
K11
81
78
M12
74
81
N13
90
109
I/O
30
51
47
57
J11
82
79
P13
75
82
T14
91
110
XTL1 OR I/O
DATA 6 (I)
52
48
58
H10
83
80
N11
78
86
P12
96
115
I/O
DATA 5 (I)
53
49
60
F10
87
84
M9
84
92
T11
102
122
I/O
CS0 (I)
54
50
61
G10
88
85
N9
85
93
R10
103
123
I/O
DATA 4 (I)
55
51
62
G11
89
86
N8
88
96
R9
108
128
I/O
DATA 3 (I)
57
53
65
F11
92
89
N7
92
102
P8
112
132
I/O
CS1 (I)
58
54
66
E11
93
90
P6
93
103
R8
113
133
I/O
DATA 2 (I)
59
55
67
E10
94
91
M6
96
106
R7
118
138
I/O
DATA 1 (I)
60
56
70
D10
98
95
M5
102
114
R5
124
145
I/O
RDY/BUSY
RCLK
61
57
71
C11
99
96
N4
103
115
P5
125
146
I/O
DIN (I)
DATA 0 (I)
38
62
58
72
B11
100
97
N2
106
119
R3
130
151
I/O
DOUT
39
63
59
73
C10
1
98
M3
107
120
N4
131
152
I/O
CCLK (I)
CCLK (O)
40
64
60
74
A11
2
99
P1
108
121
R2
132
153
CCLK (I)
WS (I)
A0
1
61
75
B10
5
2
M2
111
124
P2
135
161
I/O
CS2 (I)
A1
2
62
76
B9
6
3
N1
112
125
M3
136
162
I/O
A2
3
63
77
A10
8
5
L2
115
128
P1
140
165
I/O
A3
4
64
78
A9
9
6
L1
116
129
N1
141
166
I/O
A15
65
81
B6
12
9
K1
119
132
M1
146
172
5
A4
5
66
82
B7
13
10
J2
120
133
L2
147
173
I/O
A14
6
67
83
A7
14
11
H1
123
136
K2
150
178
I/O
A5
7
68
84
C7
15
12
H2
124
137
K1
151
179
I/O
A13
9
2
A6
17
14
G2
128
141
H2
156
184
I/O
A6
10
3
A5
18
15
G1
129
142
H1
157
185
I/O
A12
11
4
B5
19
16
F2
133
147
F2
164
192
I/O
A7
12
5
C5
20
17
E1
134
148
E1
165
193
I/O
A11
13
6
8
A3
23
20
D1
137
151
D1
169
199
I/O
A8
14
7
9
A2
24
21
D2
138
152
C1
170
200
I/O
A10
15
8
10B325
22B1
141
155
E3
173
203
I/O
A9
16
9
11
A1
26
C2142
156C2174
204
I/O
All Others
X
XC3x20A etc.
X
XC3x30A etc.
XX
X
XXX
XC3x42A etc.
X**
X
XC3x64A etc.
X**
X
XC3x90A etc.
Notes:
X**
X
XC3195A
*
(I)
**
***
****
Note:
Generic I/O pins are not shown.
For a detailed description of the configuration modes, see page 25 through page 34.
For pinout details, see page 65 through page 76.
Represents a weak pull-up before and during configuration.
INIT is an open drain output during configuration.
Represents an input.
Pin assignment for the XC3064A/XC3090A and XC3195A differ from those shown.
Peripheral mode and master parallel mode are not supported in the PC44 package.
Pin assignments for the XC3195A PQ208 differ from those shown.
Pin assignments of PGA Footprint PLCC sockets and PGA packages are not identical.
The information on this page is provided as a convenient summary. For detailed pin descriptions, see the preceding two pages.
Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a weak pull-up resistor.
Product Obsolete or Under Obsolescence
相關(guān)PDF資料
PDF描述
FMC18DREN-S13 CONN EDGECARD 36POS .100 EXTEND
FMC18DREH-S13 CONN EDGECARD 36POS .100 EXTEND
FMM28DSEF CONN EDGECARD 56POS .156 EYELET
FMM28DRKF CONN EDGECARD 56POS DIP .156 SLD
AMC30DRAS-S734 CONN EDGECARD 60POS .100 R/A PCB
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC31 制造商:TOREX 制造商全稱:Torex Semiconductor 功能描述:Temperature Controlled Voltage Regulators
XC3100 制造商:XILINX 制造商全稱:XILINX 功能描述:Logic Cell Array Families
XC3100A 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3100A/L 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3100L 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*