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| 型號(hào)： | XC3S1600E-5FGG484C |
| 廠(chǎng)商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 214/227頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN-3E 1600K 484FBGA |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | Spartan®-3E |
| LAB/CLB數(shù)： | 3688 |
| 邏輯元件/單元數(shù)： | 33192 |
| RAM 位總計(jì)： | 663552 |
| 輸入/輸出數(shù)： | 376 |
| 門(mén)數(shù)： | 1600000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 484-BBGA |
| 供應(yīng)商設(shè)備封裝： | 484-FBGA |
| 配用： | HW-XA3S1600E-UNI-G-ND - KIT DEVELOPMENT AUTOMOTIVE ECU |
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Spartan-3E FPGA Family: Functional Description
DS312 (v4.1) July 19, 2013
Product Specification
87
HDC
Output
PROM Write Enable
Connect to PROM write-enable
input (WE#). FPGA drives this
signal High throughout
configuration.
User I/O
LDC2
Output
PROM Byte Mode
This signal is not used for x8
PROMs. For PROMs with a x8/x16
data width control, connect to
PROM byte-mode input (BYTE#).
Flash PROMs. FPGA drives this
signal Low throughout
configuration.
User I/O. Drive this pin High
after configuration to use a
x8/x16 PROM in x16 mode.
A[23:0]
Output
Address
Connect to PROM address inputs.
High-order address lines may not
be available in all packages and
not all may be required. Number of
address lines required depends on
the size of the attached Flash
PROM. FPGA address generation
controlled by M0 mode pin.
Addresses presented on falling
CCLK edge.
Only 20 address lines are available
in TQ144 package.
User I/O
D[7:0]
Input
Data Input
FPGA receives byte-wide data on
these pins in response the address
presented on A[23:0]. Data
captured by FPGA on rising edge
of CCLK.
User I/O. If bitstream option
Persist=Yes, becomes
part of SelectMap parallel
peripheral interface.
CSO_B
Output
Chip Select Output. Active Low.
Not used in single FPGA
applications. In a daisy-chain
configuration, this pin connects to
the CSI_B pin of the next FPGA in
the chain. If HSWAP = 1 in a
multi-FPGA daisy-chain
application, connect this signal to a
4.7 k
Ω pull-up resistor to VCCO_2.
Actively drives Low when selecting
a downstream device in the chain.
User I/O
BUSY
Output
Busy Indicator. Typically only used
after configuration, if bitstream
option Persist=Yes.
Not used during configuration but
actively drives.
User I/O. If bitstream option
Persist=Yes, becomes
part of SelectMap parallel
peripheral interface.
CCLK
Output
Configuration Clock. Generated
by FPGA internal oscillator.
Frequency controlled by
ConfigRate bitstream generator
option. If CCLK PCB trace is long or
has multiple connections, terminate
this output to maintain signal
integrity. See CCLK Design
Not used in single FPGA
applications but actively drives. In
a daisy-chain configuration, drives
the CCLK inputs of all other
FPGAs in the daisy-chain.
User I/O. If bitstream option
Persist=Yes, becomes
part of SelectMap parallel
peripheral interface.
INIT_B
Open-drain
bidirectional I/O
Initialization Indicator. Active Low.
Goes Low at start of configuration
during the Initialization memory
clearing process. Released at the
end of memory clearing, when the
mode select pins are sampled. In
daisy-chain applications, this signal
requires an external 4.7 k
Ω pull-up
resistor to VCCO_2.
Active during configuration. If CRC
error detected during
configuration, FPGA drives INIT_B
Low.
User I/O. If unused in the
application, drive INIT_B
High.
Table 59: Byte-Wide Peripheral Interface (BPI) Connections (Cont’d)
Pin Name
FPGA Direction
Description
During Configuration
After Configuration
D
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| XC3S1600E-5FGG484I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3E FPGA Family |
| XC3S1600E-5FT256C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3E FPGA Family |
| XC3S1600E-5FT256I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3E FPGA Family |
| XC3S1600E-5FTG256C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3E FPGA Family |
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