參數(shù)資料
型號: XC3SD1800A-4CSG484LI
廠商: Xilinx Inc
文件頁數(shù): 1/101頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN 3 DSP 484CSGBGA
標準包裝: 84
系列: Spartan®-3A DSP
LAB/CLB數(shù): 4160
邏輯元件/單元數(shù): 37440
RAM 位總計: 1548288
輸入/輸出數(shù): 309
門數(shù): 1800000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 484-FBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 484-CSPBGA
DS610 October 4, 2010
Product Specification
1
Copyright 2007–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
Module 1:
Introduction
Features
Architectural Overview
Configuration Overview
General I/O Capabilities
Supported Packages and Package Marking
Ordering Information
Module 2:
The functionality of the Spartan-3A DSP FPGA family is
described in the following documents.
UG331: Spartan-3 Generation FPGA User Guide
Clocking Resources
Digital Clock Managers (DCMs)
Block RAM
Configurable Logic Blocks (CLBs)
-
Distributed RAM
-
SRL16 Shift Registers
-
Carry and Arithmetic Logic
I/O Resources
Programmable Interconnect
ISE Software Design Tools and IP Cores
Embedded Processing and Control Solutions
Pin Types and Package Overview
Package Drawings
Powering FPGAs
Power Management
UG332: Spartan-3 Generation Configuration User Guide
Configuration Overview
Configuration Pins and Behavior
Bitstream Sizes
Detailed Descriptions by Mode
-
Master Serial Mode using Platform Flash PROM
-
Master SPI Mode using Commodity Serial Flash
-
Master BPI Mode using Commodity Parallel Flash
-
Slave Parallel (SelectMAP) using a Processor
-
Slave Serial using a Processor
-
JTAG Mode
ISE iMPACT Programming Examples
MultiBoot Reconfiguration
Design Authentication using Device DNA
UG431: XtremeDSP DSP48A for Spartan-3A DSP
FPGAs User Guide
DSP48A Slice Design Considerations
DSP48A Architecture Highlights
-
18 x 18-Bit Multipliers
-
48-Bit Accumulator
-
18-bit Pre-Adder
DSP48A Application Examples
Module 3:
DC Electrical Characteristics
Absolute Maximum Ratings
Supply Voltage Specifications
Recommended Operating Conditions
Switching Characteristics
I/O Timing
Configurable Logic Block (CLB) Timing
Digital Clock Manager (DCM) Timing
Block RAM Timing
XtremeDSP Slice Timing
Configuration and JTAG Timing
Module 4:
Pin Descriptions
Package Overview
Pinout Tables
Footprint Diagrams
1
Spartan-3A DSP FPGA Family Data Sheet
DS610 October 4, 2010
Product Specification
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XC3SD1800A-4FGG676CES 制造商:Xilinx 功能描述:
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