- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4248 > XC3S5000-5FGG900C (Xilinx Inc)SPARTAN-3A FPGA 5M 900-FBGA PDF資料下載
參數(shù)資料
| 型號： | XC3S5000-5FGG900C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 17/272頁 |
| 文件大?。?/td> | 0K |
| 描述： | SPARTAN-3A FPGA 5M 900-FBGA |
| 產品培訓模塊： | Extended Spartan 3A FPGA Family |
| 標準包裝： | 27 |
| 系列： | Spartan®-3 |
| LAB/CLB數(shù)： | 8320 |
| 邏輯元件/單元數(shù)： | 74880 |
| RAM 位總計： | 1916928 |
| 輸入/輸出數(shù)： | 633 |
| 門數(shù)： | 5000000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 900-BBGA |
| 供應商設備封裝： | 900-FBGA |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁第258頁第259頁第260頁第261頁第262頁第263頁第264頁第265頁第266頁第267頁第268頁第269頁第270頁第271頁第272頁
Spartan-3 FPGA Family: Pinout Descriptions
DS099 (v3.1) June 27, 2013
Product Specification
113
X-Ref Target - Figure 41
Parallel Configuration Modes (SelectMAP)
This section describes the dual-purpose configuration pins used during the Master and Slave Parallel configuration modes,
sometimes also called the SelectMAP modes. In both Master and Slave Parallel configuration modes, D0-D7 form the
byte-wide configuration data input. See Table 75 for Mode Select pin settings required for Parallel modes.
As shown in Figure 41, D0 is the most-significant bit while D7 is the least-significant bit. Bits D0-D3 form the high nibble of
the byte and bits D4-D7 form the low nibble.
In the Parallel configuration modes, both the VCCO_4 and VCCO_5 voltage supplies are required and must both equal the
voltage of the attached configuration device, typically either 2.5V or 3.3V.
Assert Low both the chip-select pin, CS_B, and the read/write control pin, RDWR_B, to write the configuration data byte
presented on the D0-D7 pins to the FPGA on a rising-edge of the configuration clock, CCLK. The order of CS_B and
RDWR_B does not matter, although RDWR_B must be asserted throughout the configuration process. If RDWR_B is
de-asserted during configuration, the FPGA aborts the configuration operation.
After configuration, these pins are available as general-purpose user I/O. However, the SelectMAP configuration interface is
optionally available for debugging and dynamic reconfiguration. To use these SelectMAP pins after configuration, set the
Persist bitstream generation option.
The Readback debugging option, for example, requires the Persist bitstream generation option. During Readback mode,
assert CS_B Low, along with RDWR_B High, to read a configuration data byte from the FPGA to the D0-D7 bus on a rising
CCLK edge. During Readback mode, D0-D7 are output pins.
In all the cases, the configuration data and control signals are synchronized to the rising edge of the CCLK clock signal.
Table 71: Dual-Purpose Pins Used in Master or Slave Serial Mode
Pin Name
Direction
Description
DIN
Input
Serial Data Input:
During the Master or Slave Serial configuration modes, DIN is the serial configuration data input, and
all data is synchronized to the rising CCLK edge. After configuration, this pin is available as a user I/O.
This signal is located in Bank 4 and its output voltage determined by VCCO_4.
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
DOUT
Output
Serial Data Output:
In a multi-FPGA design where all the FPGAs use serial mode, connect the DOUT output of one
FPGA—in either Master or Slave Serial mode—to the DIN input of the next FPGA—in Slave Serial
mode—so that configuration data passes from one to the next, in daisy-chain fashion. This “daisy
chain” permits sequential configuration of multiple FPGAs.
This signal is located in Bank 4 and its output voltage determined by VCCO_4.
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
INIT_B
Bidirectional
(open-drain)
Initializing Configuration Memory/Configuration Error:
Just after power is applied, the FPGA produces a Low-to-High transition on this pin indicating that
initialization (i.e., clearing) of the configuration memory has finished. Before entering the User mode,
this pin functions as an open-drain output, which requires a pull-up resistor in order to produce a High
logic level. In a multi-FPGA design, tie (wire AND) the INIT_B pins from all FPGAs together so that the
common node transitions High only after all of the FPGAs have been successfully initialized.
Externally holding this pin Low beyond the initialization phase delays the start of configuration. This
action stalls the FPGA at the configuration step just before the mode select pins are sampled.
During configuration, the FPGA indicates the occurrence of a data (i.e., CRC) error by asserting
INIT_B Low.
This signal is located in Bank 4 and its output voltage determined by VCCO_4.
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
I/O Bank 4 (VCCO_4)
I/O Bank 5 (VCCO_5)
High Nibble
Low Nibble
Configuration Data Byte
D0
D1
D2
D3
D4
D5
D6
D7
0xFC =
1
0
(MSB)
(LSB)
Figure 41: Configuration Data Byte Mapping to D0-D7 Bits
相關PDF資料 |
PDF描述 |
|---|---|
| XCV200E-6BG352C | IC FPGA 1.8V C-TEMP 352-MBGA |
| XA3SD1800A-4CSG484Q | SPARTAN-3ADSP FPGA 1800K 484CSBG |
| XC6SLX100T-N3FGG484I | IC FPGA SPARTAN-6 484FPGA |
| 1-553035-8 | CONN CHAMP SHIELD RCPT 24POS |
| 828347-1 | CONN D-SUB FEM SCREW LOCK KIT |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XC3S500E-4CP132C | 制造商:Xilinx 功能描述:FPGA SPARTAN-3E 500K GATES 10476 CELLS 572MHZ 90NM 1.2V 132C - Trays |
| XC3S500E-4CP132CES | 制造商:Xilinx 功能描述: |
| XC3S500E-4CP132I | 制造商:Xilinx 功能描述:FPGA SPARTAN-3E 500K GATES 10476 CELLS 572MHZ 90NM 1.2V 132C - Trays |
| XC3S500E-4CPG132C | 功能描述:IC SPARTAN-3E FPGA 500K 132CSBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3E 標準包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計:221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應商設備封裝:388-FPBGA（23x23） 其它名稱:220-1241 |
| XC3S500E-4CPG132I | 功能描述:IC FPGA SPARTAN-3E 500K 132CSBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3E 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應商設備封裝:676-FBGA（27x27） |
發(fā)布緊急采購，3分鐘左右您將得到回復。