參數(shù)資料
型號(hào)： XC4085XL-3BG560I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 68/68頁(yè)
文件大?。?/td> 0K
描述： IC FPGA I-TEMP 3.3V 3SPD 560MBGA
產(chǎn)品變化通告： XC4000(XL,XLA,E) Discontinuation 15/Nov/2004
標(biāo)準(zhǔn)包裝： 12
系列： XC4000E/X
LAB/CLB數(shù)： 3136
邏輯元件/單元數(shù)： 7448
RAM 位總計(jì)： 100352
輸入/輸出數(shù)： 448
門(mén)數(shù)： 85000
電源電壓： 3 V ~ 3.6 V
安裝類(lèi)型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 560-LBGA，金屬
供應(yīng)商設(shè)備封裝： 560-MBGA（42.5x42.5）
R
May 14, 1999 (Version 1.6)
6-13
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
tions of the CLB, with the exception of the redenition of the
control signals. In 16x2 and 16x1 modes, the H’ function
generator can be used to implement Boolean functions of
F’, G’, and D1, and the D ip-ops can latch the F’, G’, H’, or
D0 signals.
Single-Port Edge-Triggered Mode
Edge-triggered
(synchronous)
RAM
simplies
timing
requirements. XC4000 Series edge-triggered RAM timing
operates like writing to a data register. Data and address
are presented. The register is enabled for writing by a logic
High on the write enable input, WE. Then a rising or falling
clock edge loads the data into the register, as shown in
Complex timing relationships between address, data, and
write enable signals are not required, and the external write
enable pulse becomes a simple clock enable. The active
edge of WCLK latches the address, input data, and WE sig-
nals. An internal write pulse is generated that performs the
write. See Figure 4 and Figure 5 for block diagrams of a
CLB congured as 16x2 and 32x1 edge-triggered, sin-
gle-port RAM.
The relationships between CLB pins and RAM inputs and
outputs for single-port, edge-triggered mode are shown in
The Write Clock input (WCLK) can be congured as active
on either the rising edge (default) or the falling edge. It uses
the same CLB pin (K) used to clock the CLB ip-ops, but it
can be independently inverted. Consequently, the RAM
output can optionally be registered within the same CLB
either by the same clock edge as the RAM, or by the oppo-
site edge of this clock. The sense of WCLK applies to both
function generators in the CLB when both are congured
as RAM.
The WE pin is active-High and is not invertible within the
CLB.
Note: The pulse following the active edge of WCLK (TWPS
in Figure 3) must be less than one millisecond wide. For
most applications, this requirement is not overly restrictive;
however, it must not be forgotten. Stopping WCLK at this
point in the write cycle could result in excessive current and
even damage to the larger devices if many CLBs are con-
gured as edge-triggered RAM.
X6461
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT
OLD
NEW
T
DSS
T
DHS
T
ASS
T
AHS
T
WSS
T
WPS
T
WHS
T
WOS
T
ILO
T
ILO
Figure 3:
Edge-Triggered RAM Write Timing
Table 5: Single-Port Edge-Triggered RAM Signals
RAM Signal
CLB Pin
Function
D
D0 or D1 (16x2,
16x1), D0 (32x1)
Data In
A[3:0]
F1-F4 or G1-G4
Address
A[4]
D1 (32x1)
Address
WE
Write Enable
WCLK
K
Clock
SPO
(Data Out)
F’ or G’
Single Port Out
(Data Out)
Product Obsolete or Under Obsolescence
相關(guān)PDF資料
PDF描述
XC4VLX100-10FFG1513C IC FPGA VIRTEX-4 100K 1513-FBGA
XC4VLX25-12FFG676C IC FPGA VIRTEX-4 LX 25K 676-FBGA
XC5202-5PQ100C IC - FPGA SPEED GRADE 5 COM TEMP
XC56309AG100AR2 IC DSP 24BIT 100MHZ 144-LQFP
XC56L307VF160 IC DSP 24BIT FIXED POINT 196-BGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC4085XL-3PG559C 制造商:Xilinx 功能描述:
XC4085XL-3PG559I 制造商:Xilinx 功能描述:
XC4085XLA-07BG432C 制造商:Xilinx 功能描述:
XC4085XLA-07BG560C 制造商:Xilinx 功能描述:FPGA, 3136 CLBS, 55000 GATES, 294 MHz, PBGA560
XC4085XLA-07BG560C0314 制造商:Xilinx 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*