參數(shù)資料
型號: XC4VSX55-10FFG1148C
廠商: Xilinx Inc
文件頁數(shù): 19/58頁
文件大小: 0K
描述: IC FPGA VIRTEX-4 55K 1148-FBGA
標準包裝: 1
系列: Virtex®-4 SX
LAB/CLB數(shù): 6144
邏輯元件/單元數(shù): 55296
RAM 位總計: 5898240
輸入/輸出數(shù): 640
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 1148-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1148-FCPBGA(35x35)
其它名稱: 122-1500
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
26
Input/Output Logic Switching Characteristics
Table 32: ILOGIC Switching Characteristics
Symbol
Description
Speed Grade
Units
-12
-11
-10
Setup/Hold
TICE1CK / TICKCE1
CE1 pin Setup/Hold with respect to CLK
0.58
–0.23
0.66
–0.23
0.79
–0.23
ns
TICECK / TICKCE
DLYCE pin Setup/Hold with respect to C
0.16
0.11
0.19
0.13
0.23
0.16
ns
TIRSTCK / TICKRST
DLYRST pin Setup/Hold with respect to C
–0.03
0.37
–0.02
0.45
–0.02
0.54
ns
TIINCCK / TICKINC
DLYINC pin Setup/Hold with respect to C
0.01
0.36
0.01
0.43
0.01
0.51
ns
TISRCK / TICKSR
SR/REV pin Setup/Hold with respect to CLK
1.15
–0.56
1.33
–0.56
1.59
–0.56
ns
TIDOCK / TIOCKD
D pin Setup/Hold with respect to CLK without Delay
0.24
–0.10
0.28
–0.10
0.34
–0.10
ns
TIDOCKD / TIOCKDD
D pin Setup/Hold with respect to CLK
(IOBDELAY_TYPE = DEFAULT)
6.64
–5.99
7.63
–5.99
8.84
–5.99
ns
D pin Setup/Hold with respect to CLK
(IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)(1)
0.81
–0.63
0.87
–0.63
1.09
–0.63
ns
Combinatorial
TIDI
D pin to O pin propagation delay, no Delay
0.17
0.20
0.24
ns
TIDID
D pin to O pin propagation delay
(IOBDELAY_TYPE = DEFAULT)
6.00
6.91
7.96
ns
D pin to O pin propagation delay
(IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)(1)
0.74
0.79
0.99
ns
Sequential Delays
TIDLO
D pin to Q1 pin using flip-flop as a latch without Delay
0.50
0.59
0.71
ns
TIDLOD
D pin to Q1 pin using flip-flop as a latch
(IOBDELAY_TYPE = DEFAULT)
6.90
7.94
9.21
ns
D pin to Q1 pin using flip-flop as a latch
(IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)(1)
1.07
1.18
1.45
ns
TICKQ
CLK to Q outputs
0.53
0.60
0.72
ns
TICE1Q
CE1 pin to Q1 using flip-flop as a latch, propagation delay
0.90
1.06
1.27
ns
TRQ
SR/REV pin to OQ/TQ out
1.70
2.03
2.44
ns
TGSRQ
Global Set/Reset to Q outputs
1.54
1.73
2.03
ns
Set/Reset
TRPW
Minimum Pulse Width, SR/REV inputs
0.53
0.59
0.70
ns,
Min
Notes:
1.
Recorded at 0 tap value. Refer to Timing Report for other values.
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