參數(shù)資料
型號(hào)： XC5202-5PQ100C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 26/73頁(yè)
文件大?。?/td> 0K
描述： IC - FPGA SPEED GRADE 5 COM TEMP
產(chǎn)品變化通告： XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010
標(biāo)準(zhǔn)包裝： 66
系列： XC5200
LAB/CLB數(shù)： 64
邏輯元件/單元數(shù)： 256
輸入/輸出數(shù)： 81
門(mén)數(shù)： 3000
電源電壓： 4.75 V ~ 5.25 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 100-BQFP
供應(yīng)商設(shè)備封裝： 100-QFP（14x20）
其它名稱(chēng)： Q858790
XC5202-5PQ1000C
XC5202-5PQ1000C-ND
R
XC5200 Series Field Programmable Gate Arrays
7-114
November 5, 1998 (Version 5.2)
Configuration Timing
The seven configuration modes are discussed in detail in
this section. Timing specifications are included.
Slave Serial Mode
In Slave Serial mode, an external signal drives the CCLK
input of the FPGA. The serial configuration bitstream must
be available at the DIN input of the lead FPGA a short
setup time before each rising CCLK edge.
The lead FPGA then presents the preamble data—and all
data that overflows the lead device—on its DOUT pin.
There is an internal delay of 0.5 CCLK periods, which
means that DOUT changes on the falling CCLK edge, and
the next FPGA in the daisy chain accepts data on the sub-
sequent rising CCLK edge.
shows
a
full
master/slave
system.
An
XC5200-Series device in Slave Serial mode should be con-
nected as shown in the third device from the left.
Slave Serial mode is selected by a <111> on the mode pins
(M2, M1, M0). Slave Serial is the default mode if the mode
pins are left unconnected, as they have weak pull-up resis-
tors during configuration.
Note:
Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
Figure 29: Slave Serial Mode Programming Switching Characteristics
XC5200
MASTER
SERIAL
Spartan,
XC4000E/EX,
XC5200
SLAVE
XC3100A
SLAVE
XC1700E
PROGRAM
NOTE:
M2, M1, M0 can be shorted
to Ground if not used as I/O
NOTE:
M2, M1, M0 can be shorted
to VCC if not used as I/O
M2
M0 M1
DOUT
CCLK
CLK
VCC
+5 V
DATA
CE
CEO
VPP
RESET/OE
DONE
DIN
LDC
INIT
DONE
PROGRAM
D/P
INIT
RESET
CCLK
DIN
CCLK
DIN
DOUT
M2
M0 M1
M1
PWRDN
M0
M2
(Low Reset Option Used)
4.7 K
3.3 K
3.3 K
3.3 K
3.3 K
3.3 K
3.3 K
VCC
X9003_01
N/C
Figure 28: Master/Slave Serial Mode Circuit Diagram
4 TCCH
Bit n
Bit n + 1
Bit n
Bit n - 1
3 TCCO
5 TCCL
2 TCCD
1 TDCC
DIN
CCLK
DOUT
(Output)
X5379
Description
Symbol
Min
Max
Units
CCLK
DIN setup
1
TDCC
20
ns
DIN hold
2
TCCD
0ns
DIN to DOUT
3
TCCO
30
ns
High time
4
TCCH
45
ns
Low time
5
TCCL
45
ns
Frequency
FCC
10
MHz
Product Obsolete or Under Obsolescence
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