參數(shù)資料
型號： XC5202-5PQ100C
廠商： Xilinx Inc
文件頁數(shù)： 43/73頁
文件大?。?/td> 0K
描述： IC - FPGA SPEED GRADE 5 COM TEMP
產(chǎn)品變化通告： XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010
標(biāo)準(zhǔn)包裝： 66
系列： XC5200
LAB/CLB數(shù)： 64
邏輯元件/單元數(shù)： 256
輸入/輸出數(shù)： 81
門數(shù)： 3000
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 100-BQFP
供應(yīng)商設(shè)備封裝： 100-QFP（14x20）
其它名稱： Q858790
XC5202-5PQ1000C
XC5202-5PQ1000C-ND
R
XC5200 Series Field Programmable Gate Arrays
7-130
November 5, 1998 (Version 5.2)
XC5200 Guaranteed Input and Output Parameters (Pin-to-Pin)
All values listed below are tested directly, and guaranteed over the operating conditions. The same parameters can also be
derived indirectly from the Global Buffer specifications. The delay calculator uses this indirect method, and may
overestimate because of worst-case assumptions. When there is a discrepancy between these two methods, the values
listed below should be used, and the derived values should be considered conservative overestimates.
Speed Grade
-6
-5
-4
-3
Description
Symbol
Device
Max
(ns)
Max
(ns)
Max
(ns)
Max
(ns)
Global Clock to Output Pad (fast)
T
ICKOF
(Max)
XC5202
16.9
15.1
10.9
9.8
XC5204
17.1
15.3
11.3
9.9
XC5206
17.2
15.4
11.9
10.8
XC5210
17.2
15.4
12.8
11.2
XC5215
19.0
17.0
12.8
11.7
Global Clock to Output Pad (slew-limited)
T
ICKO
(Max)
XC5202
21.4
18.7
12.6
11.5
XC5204
21.6
18.9
13.3
11.9
XC5206
21.7
19.0
13.6
12.5
XC5210
21.7
19.0
15.0
12.9
XC5215
24.3
21.2
15.0
13.1
Input Set-up Time (no delay) to CLB Flip-Flop
T
PSUF
(Min)
XC5202
2.5
2.0
1.9
XC5204
2.3
1.9
XC5206
2.2
1.9
XC5210
2.2
1.9
1.8
XC5215
2.0
1.8
1.7
Input Hold Time (no delay) to CLB Flip-Flop
T
PHF
(Min)
XC5202
3.8
3.5
XC5204
3.9
3.8
3.6
XC5206
4.4
4.3
XC5210
5.1
4.9
4.8
XC5215
5.8
5.7
5.6
Input Set-up Time (with delay) to CLB Flip-Flop DI Input
T
PSU
XC5202
7.3
6.6
XC5204
7.3
6.6
XC5206
7.2
6.5
6.4
6.3
XC5210
7.2
6.5
6.0
XC5215
6.8
5.7
Input Set-up Time (with delay) to CLB Flip-Flop F Input
T
PSU
L
(Min)
XC5202
8.8
7.7
7.5
XC5204
8.6
7.5
XC5206
8.5
7.4
XC5210
8.5
7.4
7.3
XC5215
8.5
7.4
7.2
Input Hold Time (with delay) to CLB Flip-Flop
T
PH
(Min)
XC52xx
0
00
0
Note: 1. These measurements assume that the CLB flip-flop uses a direct interconnect to or from the IOB. The INREG/ OUTREG
properties, or XACT-Performance, can be used to assure that direct connects are used. tPSU applies only to the CLB input
DI that bypasses the look-up table, which only offers direct connects to IOBs on the left and right edges of the die. tPSUL
applies to the CLB inputs F that feed the look-up table, which offers direct connect to IOBs on all four edges, as do the CLB
Q outputs.
2. When testing outputs (fast or slew-limited), half of the outputs on one side of the device are switching.
Global Clock-to-Output Delay
Q
.
Direct
Connect
IOB
CLB
FAST
BUFG
Global Clock-to-Output Delay
Q
.
Direct
Connect
IOB
CLB
BUFG
Input
Set-up
& Hold
Time
F,DI
IOB(NODELAY) Direct
Connect
CLB
BUFG
Input
Set-up
& Hold
Time
Direct
Connect
CLB
IOB(NODELAY)
F,DI
BUFG
Input
Set-up
& Hold
Time
IOB
Direct
Connect
CLB
DI
BUFG
Input
Set-up
& Hold
Time
IOB
Direct
Connect
CLB
BUFG
F
Input
Set-up
& Hold
Time
IOB Direct
Connect
CLB
BUFG
F,DI
Product Obsolete or Under Obsolescence
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