參數(shù)資料
型號(hào)： XC5204-6PC84C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 11/73頁(yè)
文件大小： 0K
描述： IC FPGA 120 CLB'S 84-PLCC
產(chǎn)品變化通告： XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010
標(biāo)準(zhǔn)包裝： 15
系列： XC5200
LAB/CLB數(shù)： 120
邏輯元件/單元數(shù)： 480
輸入/輸出數(shù)： 65
門(mén)數(shù)： 6000
電源電壓： 4.75 V ~ 5.25 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 84-LCC（J 形引線(xiàn)）
供應(yīng)商設(shè)備封裝： 84-PLCC
其它名稱(chēng)： 122-1133
R
November 5, 1998 (Version 5.2)
7-101
XC5200 Series Field Programmable Gate Arrays
7
Even if the boundary scan symbol is used in a schematic,
the input pins TMS, TCK, and TDI can still be used as
inputs to be routed to internal logic. Care must be taken not
to force the chip into an undesired boundary scan state by
inadvertently applying boundary scan input patterns to
these pins. The simplest way to prevent this is to keep
TMS High, and then apply whatever signal is desired to TDI
and TCK.
Avoiding Inadvertent Boundary Scan
If TMS or TCK is used as user I/O, care must be taken to
ensure that at least one of these pins is held constant dur-
ing configuration. In some applications, a situation may
occur where TMS or TCK is driven during configuration.
This may cause the device to go into boundary scan mode
and disrupt the configuration process.
To prevent activation of boundary scan during configura-
tion, do either of the following:
TMS: Tie High to put the Test Access Port controller
in a benign RESET state
TCK: Tie High or Low—do not toggle this clock input.
For more information regarding boundary scan, refer to the
Xilinx Application Note XAPP 017, “
Boundary Scan in
XC4000 and XC5200 Devices.“
Power Distribution
Power for the FPGA is distributed through a grid to achieve
high noise immunity and isolation between logic and I/O.
Inside the FPGA, a dedicated Vcc and Ground ring sur-
rounding the logic array provides power to the I/O drivers,
as shown in Figure 21. An independent matrix of Vcc and
Ground lines supplies the interior logic of the device.
This power distribution grid provides a stable supply and
ground for all internal logic, providing the external package
power pins are all connected and appropriately decoupled.
Typically, a 0.1
F capacitor connected near the Vcc and
Ground pins of the package will provide adequate decou-
pling.
Output buffers capable of driving/sinking the specified 8 mA
loads under specified worst-case conditions may be capa-
ble of driving/sinking up to 10 times as much current under
best case conditions.
Noise can be reduced by minimizing external load capaci-
tance and reducing simultaneous output transitions in the
same direction. It may also be beneficial to locate heavily
loaded output buffers near the Ground pads. The I/O Block
output buffers have a slew-rate limited mode (default)
which should be used where output rise and fall times are
not speed-critical.
Pin Descriptions
There are three types of pins in the XC5200-Series
devices:
Permanently dedicated pins
User I/O pins that can have special functions
Unrestricted user-programmable I/O pins.
Before and during configuration, all outputs not used for the
configuration process are 3-stated and pulled high with a
20 k
- 100 k pull-up resistor.
After configuration, if an IOB is unused it is configured as
an input with a 20 k
- 100 k pull-up resistor.
Device pins for XC5200-Series devices are described in
Table 9. Pin functions during configuration for each of the
seven configuration modes are summarized in “Pin Func-
TDI
TMS
TCK
TDO1
TDO2
TDO
DRCK
IDLE
SEL1
SEL2
RESET
UPDATE
SHIFT
BSCAN
To User
Logic
IBUF
Optional
From
User Logic
To User
Logic
X9000
Figure 20: Boundary Scan Schematic Example
GND
Ground and
Vcc Ring for
I/O Drivers
Vcc
GND
Vcc
Logic
Power Grid
X5422
Figure 21: XC5200-Series Power Distribution
Product Obsolete or Under Obsolescence
相關(guān)PDF資料
PDF描述
ABB108DHFT CONN EDGECARD 216POS .050 SMD
HMC65DRTS-S93 CONN EDGECARD 130PS DIP .100 SLD
XC5202-6PQ100C IC FPGA 64 CLB'S 100-PQFP
A1225A-1PQG100C IC FPGA 2500 GATES 100-PQFP COM
A1225A-PQ100I IC FPGA 2500 GATES 100-PQFP IND
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC5204-6PC84I 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field Programmable Gate Array (FPGA)
XC5204-6PG156C 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Field Programmable Gate Arrays
XC5204-6PG191C 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Field Programmable Gate Arrays
XC5204-6PG223C 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Field Programmable Gate Arrays
XC5204-6PG299C 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Field Programmable Gate Arrays
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*