參數(shù)資料
型號(hào)： XC5204-6PC84C
廠商： Xilinx Inc
文件頁數(shù)： 31/73頁
文件大?。?/td> 0K
描述： IC FPGA 120 CLB'S 84-PLCC
產(chǎn)品變化通告： XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010
標(biāo)準(zhǔn)包裝： 15
系列： XC5200
LAB/CLB數(shù)： 120
邏輯元件/單元數(shù)： 480
輸入/輸出數(shù)： 65
門數(shù)： 6000
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 84-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 84-PLCC
其它名稱： 122-1133
R
November 5, 1998 (Version 5.2)
7-119
XC5200 Series Field Programmable Gate Arrays
7
Notes:
1. Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in the
first data byte on the second rising edge of CCLK after INIT goes high. Subsequent data bytes are clocked in on every
eighth consecutive rising edge of CCLK.
2. The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation does
not require such a response.
3. The pin name RDY/BUSY is a misnomer. In synchronous peripheral mode this is really an ACKNOWLEDGE signal.
4.Note that data starts to shift out serially on the DOUT pin 0.5 CCLK periods after it was loaded in parallel. Therefore,
additional CCLK pulses are clearly required after the last byte has been loaded.
Figure 34: Synchronous Peripheral Mode Programming Switching Characteristics
0
DOUT
CCLK
1
2
345
6
7
BYTE
0
BYTE
1
BYTE 0 OUT
BYTE 1 OUT
RDY/BUSY
INIT
1
0
X6096
TCCL
D0 - D7
TIC
TCD
TDC
1
2
3
Description
Symbol
Min
Max
Units
CCLK
INIT (High) setup time
1
TIC
5
s
D0 - D7 setup time
2
TDC
60
ns
D0 - D7 hold time
3
TCD
0ns
CCLK High time
TCCH
50
ns
CCLK Low time
TCCL
60
ns
CCLK Frequency
FCC
8MHz
Product Obsolete or Under Obsolescence
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