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| 型號(hào)： | XC5204 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Field Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門陣列) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列（現(xiàn)場(chǎng)可編程門陣列） |
| 文件頁數(shù)： | 13/73頁 |
| 文件大?。?/td> | 598K |
| 代理商： | XC5204 |
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R
November 5, 1998 (Version 5.2)
7-95
XC5200 Series Field Programmable Gate Arrays
7
Matrix through a hierarchy of different-length metal seg-
ments in both the horizontal and vertical directions. A pro-
grammable interconnect point (PIP) establishes an electri-
cal connection between two wire segments. The PIP, con-
sisting of a pass transistor switch controlled by a memory
element, provides bidirectional (in some cases, unidirec-
tional) connection between two adjoining wires. A collec-
tion of PIPs inside the General Routing Matrix and in the
Local Interconnect Matrix provides connectivity between
various types of metal segments. A hierarchy of PIPs and
associated routing segments combine to provide a power-
ful interconnect hierarchy:
Forty bidirectional single-length segments per CLB
provide ten routing channels to each of the four
neighboring CLBs in four directions.
Sixteen bidirectional double-length segments per CLB
provide four routing channels to each of four other
(non-neighboring) CLBs in four directions.
Eight horizontal and eight vertical bidirectional Longline
Figure 15: XC5200 Interconnect Structure
X4963
Versa-
Block
GRM
Single-length Lines
Double-length Lines
Direct Connects
Longlines and Global Lines
1
Six Levels of Routing Hierarchy
1
2
3
4
5
2
3
4
Versa-
Block
GRM
Versa-
Block
GRM
Versa-
Block
GRM
Versa-
Block
GRM
Versa-
Block
GRM
Versa-
Block
GRM
Versa-
Block
GRM
Versa-
Block
GRM
Local Interconnect Matrix
Logic Cell Feedthrough
Path (Contained within each
Logic Cell)
LIM
5
6
CLB
Direct Connects
TS
LIM
4
4
4
4
4
LC3
LC2
LC1
LC0
4
4
4
4
24
6
GRM
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