參數(shù)資料
型號(hào): XC5204
廠商: Xilinx, Inc.
英文描述: Field Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門陣列)
中文描述: 現(xiàn)場(chǎng)可編程門陣列(現(xiàn)場(chǎng)可編程門陣列)
文件頁數(shù): 43/73頁
文件大小: 598K
代理商: XC5204
R
November 5, 1998 (Version 5.2)
7-125
XC5200 Series Field Programmable Gate Arrays
7
Configuration Switching Characteristics
VALID
PROGRAM
INIT
Vcc
PI
T
POR
T
ICCK
T
CCLK
T
CCLK OUTPUT or INPUT
M0, M1, M2
(Required)
DONE RESPONSE
<300 ns
<300 ns
>300 ns
RE-PROGRAM
X1532
I/O
Master Modes
Description
Symbol
T
POR
T
PI
T
ICCK
T
CCLK
T
CCLK
Min
2
6
40
640
100
Max
15
70
375
3000
375
Units
ms
Power-On-Reset
Program Latency
CCLK (output) Delay
period (slow)
period (fast)
μ
s per CLB column
μ
s
ns
ns
Slave and Peripheral Modes
Description
Symbol
T
POR
T
PI
T
ICCK
T
CCLK
Min
2
6
5
100
Max
15
70
Units
ms
Power-On-Reset
Program Latency
CCLK (input) Delay (required)
period (required)
Note:
At power-up, V
CC
must rise from 2.0 to V
CC
min in less than 15 ms, otherwise delay configuration using PROGRAM until
V
CC
is valid.
μ
s per CLB column
μ
s
ns
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