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參數(shù)資料
| 型號： | XC5210-4TQ176I |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現(xiàn)場可編程門陣列（FPGA） |
| 文件頁數(shù)： | 39/73頁 |
| 文件大?。?/td> | 598K |
| 代理商： | XC5210-4TQ176I |
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R
November 5, 1998 (Version 5.2)
7-121
XC5200 Series Field Programmable Gate Arrays
7
Notes:
1. Configuration must be delayed until INIT pins of all daisy-chained FPGAs are high.
2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte processing
and the phase of internal timing generator for CCLK.
3. CCLK and DOUT timing is tested in slave mode.
4. T
indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest T
BUSY
occurs when a byte is loaded into an empty parallel-to-serial converter. The longest T
BUSY
occurs when a new word is
loaded into the input register before the second-level buffer has started shifting out data.
This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of WS. RDY/BUSY will
go active within 60 ns after the end of WS. A new write may be asserted immediately after RDY/BUSY goes Low, but write
may not be terminated until RDY/BUSY has been High for one CCLK period.
Figure 36: Asynchronous Peripheral Mode Programming Switching Characteristics
Previous Byte D6
D7
D0
D1
D2
1
T
CA
2
T
DC
4
T
WTRB
3
T
CD
6
T
BUSY
READY
BUSY
RS, CS0
WS, CS1
D7
WS/CS0
RS, CS1
D0-D7
CCLK
RDY/BUSY
DOUT
Write to LCA
Read Status
X6097
7
4
Description
Symbol
Min
100
Max
Units
ns
Write
Effective Write time
(CSO, WS=Low; RS, CS1=High
DIN setup time
DIN hold time
RDY/BUSY delay after end of
Write or Read
RDY/BUSY active after beginning
of Read
RDY/BUSY Low output (Note 4)
1
T
CA
2
3
4
T
DC
T
CD
T
WTRB
60
0
ns
ns
ns
RDY
60
7
60
ns
6
T
BUSY
2
9
CCLK
periods
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