參數(shù)資料
型號(hào): XCF02SVO20C
廠商: Xilinx Inc
文件頁(yè)數(shù): 33/35頁(yè)
文件大?。?/td> 0K
描述: IC PROM IN SYST PRG 3.3V 20TSSOP
標(biāo)準(zhǔn)包裝: 74
可編程類型: 系統(tǒng)內(nèi)可編程
存儲(chǔ)容量: 2Mb
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
Platform Flash In-System Programmable Configuration PROMs
DS123 (v2.18) May 19, 2010
Product Specification
7
R
Platform Flash PROM TAP Characteristics
The Platform Flash PROM family performs both in-system
programming and IEEE 1149.1 Boundary-Scan (JTAG) testing
via a single 4-wire Test Access Port (TAP). This simplifies
system designs and allows standard Automatic Test
Equipment to perform both functions. The AC characteristics
of the Platform Flash PROM TAP are described as follows.
TAP Timing
Figure 4 shows the timing relationships of the TAP signals.
These TAP timing characteristics are identical for both
Boundary-Scan and ISP operations.
TAP AC Parameters
Table 9 shows the timing parameters for the TAP waveforms shown in Figure 4.
X-Ref Target - Figure 4
Figure 4: Test Access Port Timing
Table 9: Test Access Port Timing Parameters
Symbol
Description
Min
Max
Units
TCKMIN
TCK minimum clock period when VCCJ = 2.5V or 3.3V
67
ns
TMSS
TMS setup time when VCCJ = 2.5V or 3.3V
8
ns
TMSH
TMS hold time when VCCJ = 2.5V or 3.3V
25
ns
TDIS
TDI setup time when VCCJ = 2.5V or 3.3V
8
ns
TDIH
TDI hold time when VCCJ = 2.5V or 3.3V
25
ns
TDOV
TDO valid delay when VCCJ = 2.5V or 3.3V
22
ns
TCK
TCKMIN
TMSS
TMS
TDI
TDO
TMSH
TDIH
TDOV
TDIS
DS123_04_031808
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