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參數(shù)資料
| 型號： | XCF08PFSG48C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 16/35頁 |
| 文件大小： | 0K |
| 描述： | IC PROM SRL 1.8V 8M GATE 48CSBGA |
| 產(chǎn)品變化通告： | Package Assemble Change 01/Jan/2007 |
| 標(biāo)準(zhǔn)包裝： | 108 |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 存儲容量： | 8Mb |
| 電源電壓： | 1.65 V ~ 2 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 48-BFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 48-CSP（8x9） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 601 (CN2011-ZH PDF) |
| 其它名稱： | 122-1453 |
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Platform Flash In-System Programmable Configuration PROMs
DS123 (v2.18) May 19, 2010
Product Specification
23
R
AC Characteristics Over Operating Conditions When Cascading
X-Ref Target - Figure 10
Symbol
Description
XCF01S, XCF02S,
XCF04S
XCF08P, XCF16P,
XCF32P
Units
Min
Max
Min
Max
TCDF
CLK to output float delay(2,3)
when VCCO = 2.5V or 3.3V
–
25
–
20
ns
CLK to output float delay(2,3) when VCCO = 1.8V
–
35
–
20
ns
TOCK
CLK to CEO delay(3,5) when VCCO = 2.5V or 3.3V
–
20
–
20
ns
CLK to CEO delay(3,5) when VCCO = 1.8V
–
35
–
20
ns
TOCE
CE to CEO delay(3,6) when VCCO = 2.5V or 3.3V
–
20
–
80
ns
CE to CEO delay(3,6) when VCCO = 1.8V
–
35
–
80
ns
TOOE
OE/RESET to CEO delay(3) when VCCO = 2.5V or 3.3V
–
20
–
80
ns
OE/RESET to CEO delay(3) when VCCO = 1.8V
–
35
–
80
ns
TCOCE
CLKOUT to CEO delay when VCCO = 2.5V or 3.3V
–
20
ns
CLKOUT to CEO delay when VCCO = 1.8V
–
20
ns
TCODF
CLKOUT to output float delay
when VCCO = 2.5V or 3.3V
–
25
ns
CLKOUT to output float delay when VCCO = 1.8V
–
25
ns
Notes:
1.
AC test load = 50 pF for XCF01S/XCF02S/XCF04S; 30 pF for XCF08P/XCF16P/XCF32P.
2.
Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
3.
Guaranteed by design, not tested.
4.
All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
5.
For cascaded PROMs, if the FPGA’s dual-purpose configuration data pins are set to persist as configuration pins, the minimum period is
increased based on the CLK to CEO and CE to data propagation delays:
- TCYC minimum = TOCK + TCE + FPGA Data setup time
- TCAC maximum = TOCK + TCE
6.
For cascaded PROMs, if the FPGA’s dual-purpose configuration data pins become general I/O pins after configuration; to allow for the
disable to propagate to the cascaded PROMs and to avoid contention on the data lines following configuration, the minimum period is
increased based on the CE to CEO and CE to data propagation delays:
- TCYC minimum = TOCE + TCE
- TCAC maximum = TOCK + TCE
OE/RESET
CE
CLK
CLKOUT
(optional)
DATA
CEO
TOCE
TOOE
First Bit
Last Bit
TCDF
TCODF
TOCK
TCOCE
ds123_23_102203
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